Page
13 of 65
Pixel Buffering
The pixel data formatted by the video capture engine is stored into two
on-board FIFO memories. This memory serves as an elastic store for
formatted video pixel data. The FIFOs are managed by an independent
pair of controllers, implemented in the FPGA, supporting concurrent
operation. The two FIFOs are utilized in a ping-pong fashion such that
while one is being filled with new pixel data, the other is being emptied
via DMA into host memory.
Audio Buffering
The audio data formatted by the audio capture engine is stored into two
on-board FIFO memories. This memory serves as an elastic store for
formatted audio data. The FIFOs are managed by an independent
pair of controllers, implemented in the FPGA, supporting concurrent
operation. The two FIFOs are utilized in a ping-pong fashion such that
while one is being filled with new audio data, the other is being emptied
via DMA into host memory.
DMA
The DMA engines are responsible for reading formatted pixel and audio
data from the on-board FIFO memories and transferring them into host
memory via the ExpressCard interface. An intelligent scatter-gather
method is utilized, providing for an efficient use of the ExpressCard
bandwidth. The use of non-contiguous 4Kbyte buffers provides support
for the Windows operating system’s memory allocation model.
FPGA
The heart of the HD-SDI Express is a dense Field Programmable Gate
Array ( FPGA ). This FPGA implements all of the functions related to
video data capture, formatting, storage and DMA. The firmware contents
of the FPGA can be upgraded while in the field by following the
instruction outlined in Section 3 of this document entitled ‘Firmware
Upgrade from Web Site’.