IDT Tsi310TM, Руководство пользователя

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5. Configuration Registers 68
Tsi310 User Manual
80B6020_MA001_05
5.3 Register Summary
The following table provides a list of Tsi310’s registers.
Table 12: Register Summary
Register Name
Starting
Address Description See Page
PCI Configuration Space Header Registers
Vendor ID x‘00’ Manufacturer ID, assigned by the PCI Special Interest
Group 71
Device ID x‘02’ Device ID number 72
Command x‘04’ PCI bus configuration parameters 73
Status x‘06’ PCI event status 75
Revision ID x‘08’ Revision ID number 77
Class Code x‘09’ Class Code designator 77
Cache Line Size x‘0C’ PCI cache line size in DWords 78
Latency Timer x‘0D’ Latency value of bus master 79
Header Type x‘0E’ Header type 80
BIST x‘0F’ not supported 80
Base Address x‘10’ x‘14’ Optional base address register 81
Primary Bus Number x‘18’ Bus number of primary interface PCI segment 84
Secondary Bus Number x‘19’ Bus number of secondary interface PCI segment 85
Subordinate Bus Number x‘1A’ Bus number of highest PCI segment behind bridge 86
Secondary Latency Timer x‘1B’ Value of secondary latency timer as bus master 87
I/O Base x‘1C’ Base of I/O address range bits 88
I/O Limit x‘1D’ Upper address of I/O address range bits 89
Secondary Status x‘1E’ Secondary interface event status 90
Memory Base x‘20 Base of memory mapped I/O address range bits 92
Memory Limit x‘22’ Upper limit of memory mapped I/O address range bits 93
Prefetchable Memory Base x‘24’ Base of prefetchable memory address range bits 94
Prefetchable Memory Limit x‘26’ Upper limit of prefetchable memory address range bits 95