IDT Tsi310TM, Руководство пользователя, Страница: 52 / 207

3. Clocking and Reset Options 52
Tsi310 User Manual
80B6020_MA001_05
When the secondary bus is operating in PCI-X mode, an internal PLL sources the clock tree for
the secondary clock domain inside the Tsi310. The appropriate range and tuning bits for the
PLL are set once the initialization pattern is known, and an internal PLL reset signal is
deactivated to allow the PLL to begin locking to the S_CLK input frequency. The PLL requires
an allowance of 100

s to accomplish this frequency lock. An internal reset is held on the logic
in the secondary clock domain until this time period has elapsed. While the internal reset is
active, the Tsi310 will not respond to any secondary bus transactions. When the secondary bus
is operating in PCI mode, the internal PLL for the secondary interface is not used. In this case,
the internal PLL reset remains activated, keeping the PLL in the bypass mode, and the internal
logic reset is held for only five additional secondary clock cycles.
Figure 4: De-assertion of S_RST#
P_CLK
S_AD[31:00]
P_RST#
S_CLK
p_internal_rst#
2 4 5 6 7 1 3
P_Cycle
s_internal_rst#
T
pirstdly
S_PCIXCAP_PU
S_STOP#:S_TRDY#
T
xcap
S_RST#
S_DEVSEL#:
T
sirstdly
00
1XX
T
srstdly
S_REQ64#
S_CLK_STABLE
Bus parked when reset