High-speed Multifunction Boards
User Manual, Ver. 1.0, May 2015, PMH-029-10 Page 51
6.3.3
Analog Input Registers
Register 6.3.3-1 Base+0x00
Read AI FIFO Data
Bit
Description
Read
0:15
FIFO Read.
Read the Analog Input data to specified FIFO.
Yes
16:31
Reserved.
Yes
Register 6.3.3-2 Base+0x04
AI FIFO Control Status
Bit
Description
Read
Write
0:10
FIFO Count and Clear.
Read the FIFO data count to specified
FIFO. Write a 0 to clear data to specified FIFO.
Yes
Yes
11
FIFO Full.
Reading a 1 indicates a FIFO status is full.
Yes
No
12
FIFO Empty.
Reading a 1 indicates a FIFO status is empty.
Yes
No
13:31
Reserved.
Yes
No
Register 6.3.3-3 Base+0x08
Analog Input Internal Clock Control/Status
Bit
Description
Read
Write
0:31
Set Div Clock.
Indicates the (WORD)((Base Clock/Sampling
Rate)-1) to set internal pacer clock during an Analog Input
operation.
Yes
Yes
Register 6.3.3-4 Base+0x0C
AI Scan Mode Control/Status
Bit
Description
Read
Write
0:3
Total Scan Channel Number.
Indicates the number of channels
to MagicScan. Writing a N indicates an 0 to N channels. Ex.
Writing a 15 indicates 0 to 15 channel. Writing an 9 indicates 0
to 9 channel.
Yes
Yes
4:6
Reserved.
Yes
No
7
Analog Input Range.
Writing 1 indicates a bipolar 10 V, Writing 0
indicates a bipolar 5 V.
Yes
Yes
8
Pacer Trigger Start Status.
Yes
No
9
ADC Status.
Reading a 1 indicates a ADC Status is ready. Reading
a 0 indicates a ADC Status is busy.
10:11
Reserved.
Yes
No
12
Pacer Trigger Source.
Writing 1 indicates an external clock,
Writing 0 indicates an external clock.
Yes
Yes
13:31
Reserved.
Yes
No