High-speed Multifunction Boards
User Manual, Ver. 1.0, May 2015, PMH-029-10 Page 48
6.3
Bar 0 (MMIO)
6.3.1
Interrupt and Initialize Control/Status Registers
Register 0-1 Base+0x18
Interrupt Control/Status
Bit
Description
Read
Write
0
Enable Interrupt.
Write a 1 enables interrupt when DMA done
or FIFO level trigger.
Yes
Yes
1
Interrupt Status.
Reading a 1 indicates an interrupt is complete.
Yes
No
2
Set Interrupt Mode.
Write a 1 enables DMA down interrupt.
Write a 0 enable FIFO level trigger.
Yes
No
3
1
Yes
No
4:7
FIFO Trigger Level.
Write a 0 indicates 32, write a 1 indicates 64,
write a 2 indicates 128, write a 3 indicates 256, write a 4
indicates 512, write a 5 indicates 1024, write a 6 is 1536 and
write 7 to 15 is 32.
Yes
Yes
8
Enable AI Post Trigger Mode.
Writing a 1 indicates a post-trigger
mode for Analog Input when DTRG0 interrupt enables.
Yes
Yes
9
Enable AI Pre Trigger Mode.
Writing a 1 indicates a pre-trigger
mode for Analog Input when DTRG1 interrupt enables.
Yes
Yes
10
1
Yes
No
11
1
Yes
No
12
Enable DTRG0 External Trigger Interrupt.
Writing a 1 enable
external signal interrupt from DTRG0.
Yes
Yes
13
DTRG0 Interrupt Status.
Reading a 1 indicates an external
trigger interrupt is complete for DTRG0.
Yes
No
14
Enable DTRG1 External Trigger Interrupt.
Writing a 1 enable
external signal interrupt from DTRG1.
Yes
Yes
15
DTRG1 Interrupt Status.
Reading a 1 indicates an external
trigger interrupt is complete for DTRG1.
Yes
No
16:31
Reserved.
Yes
No