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應用程式函式庫
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B.2 Mode Register1: WR1
Each axis is with mode register WR1. The axis specified by NOP command
or the condition before decides which axis’ s register will be written.
The register consists of the bit for setting enable / disable and enable
logical levels of input signal STOP2~STOP0 (decelerating stop / sudden
stop during the driving) and bit for occurring the interrupt enable / disable.
Once SP2~SP0 are active, when the fixed / continuous driving starts, and
also when STOP signal becomes the setting logical level, the decelerating
stop will be performed during the acceleration / deceleration driving and the
sudden stop will be performed during the constant speed driving.
WR1
D5,3,1 SPm-E The bit for setting enable / disable of driving stop input signal
STOPm 0: disable, 1: enable
D4,2,0 SPm-L
The bit for setting enable logical levels for input signal STOPm 0:
stop on the Low level, 1:stop on the Hi
level
D6
EPCLR
When driving stops triggered by the nSTOP2 signal, the real
position counter is cleared. When the nSTOP2
signal is changed to the Active level while this bit is set to 1, the
driving stops and the real position counter
(EP) is cleared. The WR1/D5(SP2-E) bit must be set to 1 and the
Enable level must be set in the
WR1/D4(SP2-L)
bit.
D7
EPINV Reverse increase / decrease of real position counter.