IBM PPC440X5 CPU Core, Руководство пользователя

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User’s Manual
PPC440x5 CPU Core Preliminary
Page 92 of 589
init.fm.
September 12, 2002
11. Initialize interrupt resources
1. Initialize IVPR to specify high-order address of the interrupt handling routines
Make sure that the corresponding address region is covered by a TLB entry (or entries)
2. Initialize IVOR0–IVOR15 registers (individual interrupt vector addresses)
Make sure that the corresponding addresses are covered by a TLB entry (or entries)
Because the low order four bits of IVOR0–IVOR15 are reserved, the values written to those bits are
ignored when the registers are written, and are read as zero when the registers are used. Therefore,
all interrupt vector offsets are implicitly aligned on quadword boundaries. Software must take care to
assure that all interrupt handlers are quadword-aligned.
3. Setup corresponding memory contents with the interrupt handling routines
4. Synchronize any program memory changes as required. (See Self-Modifying Code on page 106 for
more information on the instruction sequence necessary to synchronize changes to program memory
prior to executing the new instructions.)
12. Configure debug facilities as desired
1. Write DBCR1 and DBCR2 to specify IAC and DAC event conditions
2. Clear DBSR to initialize IAC auto-toggle status
3. Initialize IAC1–IAC4, DAC1–DAC2, DVC1–DVC2 registers to desired values
4. Write MSR[DWE] to enable Debug Wait mode (if desired)
5. Write DBCR0 to enable desired debug mode(s) and event(s)
6. Context synchronize to establish new debug facility context (isync)
13. Configure timer facilities as desired
1. Write DEC to 0 to prevent Decrementer exception after TSR is cleared
2. Write TBL to 0 to prevent Fixed Interval Timer and Watchdog Timer exceptions after TSR is cleared,
and to prevent increment into TBH prior to full initialization
3. CCR1[TCS] (Timer Clock Select) can be initialized here, or earlier with the rest of the CCR1.
4. Clear TSR to clear all timer exception status
5. Write TCR to configure and enable timers as desired
Software must take care with respect to the enabling of the Watchdog Timer reset function, as once
this function is enabled, it cannot be disabled except by reset itself
6. Initialize TBH value as desired
7. Initialize TBL value as desired
8. Initialize DECAR to desired value (if enabling the auto-reload function)
9. Initialize DEC to desired value
14. Initialize facilities outside the processor core which are possible sources of asynchronous interrupt
requests (including DCRs and/or other memory-mapped resources)
This must be done prior to enabling asynchronous interrupts in the MSR
15. Initialize the MSR to enable interrupts as desired