IBM PPC440X5 CPU Core, Руководство пользователя

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User’s Manual
PPC440x5 CPU Core Preliminary
Page 106 of 589
cache.fm.
September 12, 2002
lines beyond the one in progress at the time that the ICC determines that it needs to request a new line will be
abandoned. For example, if CCR0[ICSLC] is set to 3, and the ICC is in the middle of receiving the data for the
first of the three speculative lines at the time that the new instruction cache miss request is received from the
instruction unit, the second and third lines of the speculative burst will be abandoned, and whether the first of
the speculative lines is abandoned is controlled by CCR0[ICSLT].
Since cache lines contain 32 bytes, there are four doublewords in each cache line. Thus, CCR0[ICSLT] can
be set to a value from 0 to 3. If CCR0[ICSLT] = 0, the current line fill will be completed regardless of how
many doublewords have already been received. Similarly, if CCR0[ICSLT] = 3, the current line fill will be
abandoned if only two or fewer doublewords have been received by the ICC.
If at the time that the ICC determines that it needs to request a new line and abandon a speculative burst
request, the ICC has still not received all of the data associated with the initial cache line request which
prompted the speculative burst request, then this initial cache line is considered the “current” line, and the
speculative burst request will be abandoned without filling any of the speculative lines, regardless of the
setting of CCR0[ICSLT]. The filling of the initial cache line will be completed, however, as the PLB protocol
does not provide for the abandonment of the cache line (non-burst) request type.
Regardless of the value of CCR0[ICSLT], any time that a cache line fill is abandoned such that all of the data
for that cache line is not received, the line may still be used to bypass instructions to the instruction unit, but it
will not be written into the instruction cache, and it will be overwritten in the ICLFD buffer as soon as instruc-
tions for a new line begin arriving from the PLB.
4.2.3 Instruction Cache Coherency
In general, the PPC440x5 does not automatically enforce coherency between the instruction cache, data
cache, and memory. If the contents of memory location are changed, either within the data cache or within
memory itself, and whether by the PPC440x5 core through the execution of store instructions or by some
other mechanism in the system writing to memory, software must use cache management instructions to
ensure that the instruction cache is made coherent with these changes. This involves invalidating any obso-
lete copies of these memory locations within the instruction cache, so that they will be reread from memory
the next time they are referenced by program execution.
4.2.3.1 Self-Modifying Code
To illustrate the use of the cache management instructions to enforce instruction cache coherency, consider
the example of self-modifying code, whereby the program executing on the PPC440x5 core stores new data
to memory, with the intention of later branching to and executing this new “data,” which are actually instruc-
tions.
The following code example illustrates the required sequence for software to use when writing self-modifying
code. This example assumes that addr1 references a cacheable memory page.
stw regN, addr1 # store the data (an instruction) in regN to addr1 in the data cache
dcbst addr1 # write the new instruction from the data cache to memory
msync # wait until the data actually reaches the memory
icbi addr1 # invalidate addr1 in the instruction cache if it exists
msync addr1 # wait for the instruction cache invalidation to take effect
isync # flush any prefetched instructions within the ICC and instruction
# unit and re-fetch them (an older copy of the instruction at addr1
# may have already been fetched)