IBM PPC440X5 CPU Core, Руководство пользователя

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User’s Manual
Preliminary PPC440x5 CPU Core
overview.fm.
September 12, 2002
Page 33 of 589
The translation lookaside buffer (TLB) is the primary hardware resource involved in the control of translation,
protection, and storage attributes. It consists of 64 entries, each specifying the various attributes of a given
page of the address space. The TLB is fully-associative; the entry for a given page can be placed anywhere
in the TLB. The TLB tag and data memory arrays are parity protected against soft errors; if a parity error is
detected, the CPU will cause a machine check exception.
Software manages the establishment and replacement of TLB entries. This gives system software significant
flexibility in implementing a custom page replacement strategy. For example, to reduce TLB thrashing or
translation delays, software can reserve several TLB entries for globally accessible static mappings. The
instruction set provides several instructions for managing TLB entries. These instructions are privileged and
the processor must be in supervisor state in order for them to be executed.
The first step in the address translation process is to expand the effective address into a virtual address. This
is done by taking the 32-bit effective address and appending to it an 8-bit Process ID (PID), as well as a 1-bit
“address space” identifier (AS). The PID value is provided by the PID register (see Chapter 5, “Memory
Management”). The AS identifier is provided by the Machine State Register (MSR, see Chapter 6, “Interrupts
and Exceptions,” which contains separate bits for the instruction fetch address space (MSR[IS]) and the data
access address space (MSR[DS]). Together, the 32-bit effective address, the 8-bit PID, and the 1-bit AS form
a 41-bit virtual address. This 41-bit virtual address is then translated into the 36-bit real address using the
TLB.
The MMU divides the address space (whether effective, virtual, or real) into pages. Eight page sizes (1KB,
4KB, 16KB, 64KB, 256KB, 1MB, 16MB, 256MB) are simultaneously supported, such that at any given time
the TLB can contain entries for any combination of page sizes. In order for an address translation to occur, a
valid entry for the page containing the virtual address must be in the TLB. An attempt to access an address
for which no TLB entry exists causes an Instruction (for fetches) or Data (for load/store accesses) TLB Error
exception.
To improve performance, both the instruction cache and the data cache maintain separate “shadow” TLBs.
The instruction shadow TLB (ITLB) contains four entries, while the data shadow TLB (DTLB) contains eight.
These shadow arrays minimize TLB contention between instruction fetch and data load/store operations. The
instruction fetch and data access mechanisms only access the main 64-entry unified TLB when a miss occurs
in the respective shadow TLB. The penalty for a miss in either of the shadow TLBs is three cycles. Hardware
manages the replacement and invalidation of both the ITLB and DTLB; no system software action is required.
Each TLB entry provides separate user state and supervisor state read, write, and execute permission
controls for the memory page associated with the entry. If software attempts to access a page for which it
does not have the necessary permission, an Instruction (for fetches) or Data (for load/store accesses)
Storage exception will occur.
Each TLB entry also provides a collection of storage attributes for the associated page. These attributes
control cache policy (such as cachability and write-through as opposed to copy-back behavior), byte order
(big endian as opposed to little endian), and enabling of speculative access for the page. In addition, a set of
four, user-definable storage attributes are provided. These attributes can be used to control various system-
level behaviors, such as instruction compression using IBM CodePack technology. They can also be config-
ured to control whether data cache lines are allocated upon a store miss, and whether accesses to a given
page should use the “normal” or “transient” portions of the instruction or data cache (see Chapter 4, “Instruc-
tion and Data Caches,” for detailed information about these features).
Chapter 5, “Memory Management,” describes the PPC440x5 MMU functions.