IBM PPC440X5 CPU Core, Руководство пользователя

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User’s Manual
Preliminary PPC440x5 CPU Core
init.fm.
September 12, 2002
Page 91 of 589
care must be taken during the initialization sequence to prevent any such context synchronizing opera-
tions (such as interrupts and the isync instruction) until after this step is completed, and an architected
TLB entry has been established in the TLB. Particular care should be taken to avoid store operations,
since write permission is disabled upon reset, and an attempt to execute any store operation would result
in a Data Storage interrupt, thereby invalidating the shadow TLB entry.
1. Initialize MMUCR
- Specify TID field to be written to TLB entries
- Specify TS field to be used for TLB searches
- Specify store miss allocation behavior
- Enable/disable transient cache mechanism
- Enable/disable cache locking exceptions
2. Write TLB entry for initial program memory page
- Specify EPN, RPN, ERPN, and SIZE as appropriate for system
- Set valid bit
- Specify TID = 0 (disable comparison to PID) or else initialize PID register to matching value
- Specify TS = 0 (system address space) or else MSR[IS,DS] must be set to correspond to TS=1
- Specify storage attributes (W, I, M, G, E, U0–U3) as appropriate for system
- Enable supervisor mode fetch, read, and write access (SX, SR, SW)
3. Initialize PID register to match TID field of TLB entry (unless using TID = 0)
4. Setup for subsequent MSR[IS,DS] initialization to correspond to TS field of TLB entry
Only necessary if TS field of TLB entry being set to 1 (MSR[IS,DS] already reset to 0)
- Write new MSR value into SRR1
- Write address from which to continue execution into SRR0
5. Setup for subsequent change in instruction fetch address
Only necessary if EPN field of TLB entry changed from the initial value (EPN
0:19
≠
0xFFFFF)
- Write initial/new MSR value into SRR1
- Write address from which to continue execution into SRR0
6. Initialize or invalidate all other TLB entries as desired
7. Context synchronize to invalidate shadow TLB contents and cause new TLB contents to take effect
- Use isync if not changing MSR contents and not changing the effective address of the rest of
the initialization sequence
- Use rfi if changing MSR to match new TS field of TLB entry (SRR1 will be copied into MSR, and
program execution will resume at value in SRR0)
- Use rfi if changing next instruction fetch address to correspond to new EPN field of TLB entry
(SRR1 will be copied into MSR, and program execution will resume at value in SRR0)
Instruction and data caches will now begin to be used, if the corresponding TLB entry has been setup
with the caching inhibited storage attribute set to 0. Initialization software can now branch outside of
the initial 4KB memory region as controlled by the address and size of the new TLB entry and/or any
other TLB entries which have been setup.