603 Hardware Specifications, REV 2
11
Preliminary—Subject to Change without Notice
Figure 4. Output Timing Diagram
SYSCLK
12
14
13
15
16
16
ALL OUTPUTS
(Except TS, ABB
TS
ARTRY
ABB, DBB
VM
VM
VM = Midpoint Voltage (1.4 V)
DBB, ARTRY)
15
VM
13
20
18
17
21
19