Chapter 6 – Platform Management Option
0818D
User’s
Guide
6-2
CMC Board
Microcontroller
IPMI
OS, IPMI,
Control
Apps
Buffer
Data,
Event
Log
Battery
Backup
FlashROM
RAM
EEPROM
Host SBC
LM75
(up to 8)
Voltage
Reader(7)
Digital IO
(3 in / 3 out)
Relay
Output (3)
Display/Status
(4 out / 2 in)
RS-232
IPMB0
Figure 6-1. Block Diagram of a Chassis Management Controller
Figure 6-2 shows the I2C ports assignment between the CMC
controller chip (e.g., VSC215) and the CompactPCI backplane.
CMC Controller Chip
(eg. VSC215)
CMC
Backkplane
Connector
H1 H2 H3 H4
H1 - H4: 1x5 pin header
pin1: SCL
pin2: GND
pin3: SDA
pin4: +5V (IPMB PWR)
pin5: (ALERT)
I2C1_x
I2C2_x
I2C3_x
to backplane IPMB0
to backplane IPMB1
LM75
Local I2C
I2C2
I2C3
I2C0
I2C1
Figure 6-2. I2C Ports Assignment
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