6
XP68-03-LX45 v1.0
3.
JTAG connection
JTAG signal is led out to pins as below. Please prepare an external connector to
access to the FPGA and the configuration device. JTAG buffer or other process is
needed as the situation demands.
When those pins are unused, please connect them to GND and do not leave them open.
If consumption current caused by on-board pull-up or pull-down resistors would be
a problem, connect the signals to GND or V33P according to the circuit design.
* Please be careful to avoid wrong wiring.
Pin
Signal
Dir
32
TCK
IN
33
TDO
OUT
34
TMS
IN
37
TDI
IN
JTAG Connection Example
4.
FPGA Configuration
To configure the FPGA via JTAG directly, select FPGA icon detected by
Boundary-Scan and assign a bit-stream file in iMPACT.
If configuration is completed successfully, the DONE LED will light up.
