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3-12 Memory System
J Class Technical Reference
registers, internal interconnects, and execution units, system wide resources, such as
processor–memory–I/O interconnect bus arbitration and cache coherency responses, and memory
system resources, memory banks and DRAM Data busses.
The following behaviors are assumed to predict system performance.
Uniform distribution of memory addresses.
Homogeneity – Transactions arrival rate is a function of memory retirement rate and queue length.
Transaction Flow Balance – While not true in every state, the arrival rate is assumed to closely
approximate the retirement rate through the memory system.
The system has reached a state of equilibrium: the steady–state.
Transaction arrival is Poisson
The following analysis presumes that the memory system has the single greatest ability to limit the
system’s throughput and processing power. Simply, it is assumed that the CPU, and/or IO system, is
constructed in a manner that it will always exceed the memory system’s ability to retire transactions.
Therefore, the rate at which transactions are issued is primarily a function of their rate of retirement. So, as
the retirement rate increases, the rate of issue also increases. However, the average rate at which
transactions arrive for service must never exceed, and should truly be less than, the average rate at which
they retire for a stable queue. Still, this positions the memory system as the primary system throughput
and processing power limiter.
Memory System Characteristics
Memory system performance is normally characterized in terms of average cycle time and latency. While
sometime independent, they are often related. As an example, the cycle time, or retirement rate, of the
memory system affects the average latency in a queued system. An increased cycle time also increases the
time a transaction sits in queue, thereby increasing the time it takes to complete the transaction from the
point of issue.
The simplest, and most common, tactic used in characterizing memory system performance is to state
maximum bandwidth and idle system latency values. While these are important characteristics, they do
not sufficiently consider enough of the important aspects affecting memory system performance. A
method capturing the effects of bank cycle time, and bus cycle time, as a functions of resource contention,
would be of more interest.
Transaction Behavior
As stated earlier, the transactions are assumed to be uniformly distributed throughout memory. This is a
reasonable assumption for our purposes, generally predicting modest memory system performance,
especially in an MP system where the locality of reference is more random compared to a uniprocessor
system. However, many memory intensive workloads do actually stride, rather than wander, through
memory, thereby attaining greater throughputs, often approaching the maximum the system affords.
For this modest approximation, the rate at which transactions cycle through the system is assumed to be
primarily a function of the memory system’s ability to retire them. The transaction cycle time of the
system is assumed to be primarily a function of the transaction issue rate, which is a function of queue
sizes and retirement rate. For this analysis, a somewhat loose correlation is assumed between the issue
and retirement latency of a prior transaction. Therefore, the number of “live” transactions closely
approximates the maximum number of queue slots available. Also, transaction flow balance is assumed,
with the average issue rate closely approximating the retirement rate.