HP Visualize J200, Справочное руководство

Страница: 51 / 99

3-16 Memory System
J Class Technical Reference
For example, the J Class design limits the number of CCC queue entries to 10. From the above formula,
the average issue rate can then be determined to be 10/11, or ~91%, of the service rate. Of course these are
very rough approximations.
Bandwidth Considerations
The Fast Page Mode Graph (Figure 3–6) shows a difference between the maximum bandwidth, or
minimum cycle time, data points, and the calculated contention–factored data points. As shown, the
largest J Class configuration, with 16 banks and 2 DRAM Data busses, produces a 4 clock per data cycle
time, or 480 MB/second throughput. This example shows that memory bandwidth can be limited by two
factors: bank contention and DRAM Data bus contention.
The EDO Graph shows an improvement over the Fast Page Mode configuration. The 16 bank, 2 DRAM
Data bus configuration produces a 3.5 clock per data cycle time, or 540 MB/second throughput. This
example shows that memory bandwidth can be improved by reducing the level of bank contention
(shorter DRAM cycle time) and DRAM Data bus contention (smaller “slot timing”).
Bank Limitations
The number of memory banks significantly affects the ACT of the memory system. As more banks are
added, the ACT asymptotically approaches the minimum cycle time. In general, the memory system
depends on large numbers of memory banks to generate high data throughputs, via reduced bank
contention.
In a typical 128 MB configuration, it is possible that only two banks of memory are available – when
using 16 Mbit, 4Mbit x 4, DRAM technology. In this configuration, the memory system ACT is able only
to produce 256 MB/second, which is a direct result of the small number of memory banks. This situation
can be improved by using 4Mbit DRAMs instead, thereby creating four times the number of banks per
MB. But this creates a potential future capacity upgrade problem and may not be cost effective in the long
run.
Bus Limitations
Another factor limiting memory performance involves the small number of DRAM Data busses used.
The right–most vector represents the single bus design, while the left most vector represents the best
possible case with two busses.
Memory Latency Considerations
Note:
This section is even more academic than the bandwidth estimations above, but included
for completeness. In general, this section is simply attempting to show that memory latency is also a
function of bank and bus contention, and may be improved through the addition of these resources.