HP KAYAK XM600, Техническое справочное руководство

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2 System Board
Memory Controller Hub (MCH) 82820
Read/Write Buffers
The MCH defines a data buffering scheme to support the required level of
concurrent operations and provide adequate sustained bandwidth between
the DRAM subsystem and all other system interfaces (CPU, AGP and PCI).
System Clocking
The MCH operates the host interface at 100 MHz or 133 MHz, PCI at 33 MHz
and AGP at 66/133 MHz. Coupling between all interfaces and internal logic is
done in a synchronous manner. The clocking scheme uses an external clock
synthesizer (which produces reference clocks for the host, AGP and PCI
interfaces).
I/O APIC
I/O APIC is used to support dual processors as well as enhanced interrupt
processing in the single processor environment. The MCH supports an
external status output that can be used to control synchronization of
interrupts in configurations that use ICH with stand-alone I/O APIC
components.