HP KAYAK XM600, Техническое справочное руководство

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2 System Board
Memory Controller Hub (MCH) 82820
AGP 4x Bus
The AGP bus is a dedicated bus for the graphics subsystem, which meets the
needs of high quality 3D graphics applications. It has a direct link to the
MCH.
The AGP bus is based upon a 133 MHz, 32-bit PCI bus architecture, to which
several signal groups provide AGP-specific control and transfer
mechanisms.
Pipelining is added along with special sideband signals, increasing the
efficiency of the AGP bus. Thus, you come closer to the theoretical
maximum bandwidth. Although the maximum transfer rate is never
exceeded, the overall transfer rate is increased.
AGP specific transactions always use pipelining. This control mechanism
increases the bus efficiency for data transfer. Sideband Addressing (SBA)
may also be used by AGP transaction requests which also increases the bus
efficiency for data transfer. These two mechanisms can combine
independently to pipelining, which leads to the following operating modes:
•
FRAME- based AGP. Only the PCI protocol is used: 66 MHz, 32-bits, 3.3
V, 266 MB/s peak transfer rate.
•
AGP 1X with pipelining, sideband addressing can be added: uses 66 MHz,
32-bits, 3.3 V, increased bus efficiency, 266 MB/s peak transfer rate.
•
AGP 2X with pipelining, sideband addressing can be added: 66 MHz
double clocked, 32-bits, 3.3 V, increased bus efficiency, 533 MB/s peak
transfer rate.
•
AGP 4X with pipelining, sideband addressing can be added: 133 MHz quad
clocked, 32-bits, 1.5 V, increased bus efficiency, 1066 MB/s peak transfer
rate