HP KAYAK XM600, Техническое справочное руководство

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2 System Board
Memory Controller Hub (MCH) 82820
AGP PCI Bus
Implementation
Main Memory Controller
The main memory controller is integrated in the MCH supporting a single
Direct Rambus channel.
DRAM Interface
The MCH provides optional Host bus error checking for data, address,
request and response signals. 300 MHz, 356 MHz and 400 MHz Direct
Rambus devices are supported in any of 64, 128 or 256 Mbit technology.
64 and 128 Mbit RDRAMs use page sizes of 1 kbyte, while 256 Mb devices
target 1 kbyte or 2 kbyte pages.
A maximum number of 32 Rambus devices (64 Mb technology implies 512
Mb maximum in 16 Mb increments, 256 Mb technology implies 1 GB
maximum in 256 Mb increments) are supported on the Direct Rambus
channel without external logic.
The MCH also provides optional data integrity features including ECC in the
memory array. During DRAM writes, ECC is generated on a QWord (64 bit)
basis. During DRAM reads, the MCH supports multiple-bit error detection
and single-bit error correction when the ECC mode is enabled.
Pentium III Processor
GX-Device 1
AGP Port
Interface
I/O Controller Hub
(ICH) 82801AA
820
Memory
Controller Hub
(MCH)
82820
AGP
Connector
AGP 4x Bus
(133 MHz)