Table 2-1. Description of the Status Bits (Continued)
Bit
Status
Signals
Description
4 - 7
BE0# - BE3#
Byte Enables, with BE0# the least significant byte and BE3#
the most significant byte. For opcode fetches, the
microprocessor will fetch four bytes unless BS16# is asserted.
When BS16# is asserted, the microprocessor fetches two bytes.
8
BS16#
If this signal is low for a 16-bit bus cycle, the microprocessor
will perform an additional bus cycle if required. For instance,
if BS16# was low during a memory write with all byte enable
(BE# ) lines low, the microprocessor would perform a second
bus cycle using the data from the upper two bytes of the data
bus of the first cycle, on the lower two bytes of the data bus for
the second cycle.
9
NA# *
When this signal is low it indicates that the system is requesting
the next address from the microprocessor.
10
LOCK#
When this signal is low it indicates that the microprocessor has
the bus locked to prevent interruption by other bus devices.
11
ERROR# *
When this signal is low it indicates that the previous
coprocessor instruction generated a coprocessor error.
12
PEREQ *
When this signal is high it requests that the microprocessor
perform a data operand transfer for a coprocessor extension.
13
BU SY# *
When this signal is low it indicates the coprocessor is still
executing an instruction.
14
ADS# *
When this signal is low it indicates a valid bus cycle and address
is available on the microprocessor pins.
15
READY# *
When this signal is low it terminates the bus cycle. This signal
is ignored during bus hold acknowledge.
* These signals are used for timing analysis purposes when the H P E 2444A is operating in the timing mode.
Analyzing the Intel 80386DX/DXL
HP E2444A
2-6
80386DX/DXL Preprocessor Interface
