HP 5004A, Руководство по эксплуатации и обслуживанию

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Model
Service
8-88. Display Control (Data Signal Path Continued)
8-89. The 16-line signature output of the word generator
is
applied to the inputs of registers
U15, U16, U13, and U14 which drive a memory used as a character decoder. The output of
i s applied to the four LED seven-segment digits on the display assembly.
8-90. Signature Comparator (UNSTABLE Signature Lamp)
8-91. As each signature is applied to the character decoder, it is also stored in memory
When the next signature is received it i s compared with the previous signature in U23. If
the two signatures are different, U23 outputs a pulse to U7A which is sent to pulse-on the UN-
STABLE SIGNATURE lamp on the display assembly, A2. If succeeding signals are identical,
U23 does not send a pulse to the lamp. The comparator receives a low-frequency strobe signal
from which controls the timing of a store and compare cycle.
8-92. Oscillator
8-93. U28 is a low-frequency (.6 Khz) square wave oscillator. The output of U28 i s used for
the test circuit and to scan the displays.
8-94. Display Scan
8-95. The front-panel-swiched self-test circuit includes U27, U25, U29, and U17. The four-bit
counters, U27 and U25 are cycled by a signal from the self-test oscillator, U28, through U26.
Outputs of
and U26 address memory U29 which supplies START and STOP signals in the
self-test mode. All possible states of the gate control circuit are exercised in each self-test cycle
to check proper operation. Self-test signals are applied to the inputs of the
to allow all
circuits to be tested. Part of the test besides specific signatures
i s
to apply trash to U17 which
will exercise all seven segments of each display digit.
8-98. Test Switch
8-99. The test switch on the main assembly allows all feedback paths
in the to be opened for complete signature analysis testing, with a second Signa-
ture Analyzer. (Refer to the troubleshooting procedures in this section.)
8-100.
SIGNAL 'TIMING
8-101. Figure 8-5 shows the timing relationship between the input, CLOCK, START, DATA,
and STOP signals. The diagram shows that the START signal must transition from low to high
before the gate will open, and data in the middle level
is accepted as the preceding condition.
Figure 8-5. Signals Timing
CLOCK
1 1 1 1
X
1
START
STOP
DATA
DATA X
ACCEPTED