HP 5004A, Руководство по эксплуатации и обслуживанию

Страница: 63 / 74

Model
Service
8-76. ECL-to-TTL Level Converters
8-77. After the edge select switches the gating signals are applied to four separate
TTL level converters. (The CLOCK signal
i s
applied to two separate converters, and B,
for two separate paths.) The outputs of the START and STOP level converters are applied to
latches which are controlled by the CLOCK signal. The latches outputs are applied to the gate
control circuit.
8-78. Control
8-79. The input START and STOP signals are processed in the gate control circuit to produce
a definite time window during which data is received by the word generator (described later).
Operation of the gate control circuit i s described in the following paragraph.
8-80. State Diagram
8-81. Figure
8-4
is a state diagram of the functioning of the gate control circuits. NOTE:
tive-true logic i s used. The state normally occurs: when the has power switched
on, or when the data probe RESET switch i s pressed, or when a STOP and START pulse are re-
ceived in RUN mode. In the
state, if START is the state will change to ARMED. In
the ARMED state the is ready to receive a START pulse and proceed to either RUN mode.
(Note that if a STOP pulse is received, the state will be intermediate RUN; and to progress to
full RUN, STOP must be
From full RUN the state will return to INITIAL if START and STOP
pulses are received. If START remains at and a STOP pulse i s received, the state returns to
ARMED. The HOLD state occurs when the HOLD switch is in and a STOP pulse i s received in
the full RUN mode. In the HOLD state, the data probe RESET switch must be pressed to return
to the
state. All modes except HOLD have no-change conditions. For example in the
ARMED state if the START line remains at 0, the will not change to With proper
START, STOP, and CLOCK signals the gate control proceeds through the states repetitively.
The gate control circuit output starts and stops the word generator, and provides the on-off
control of the GATE lamp to show when the START and STOP signals are received and
implemented.
8-82. Data Signal Flow
8-83. In normal operation, data signals from the unit being tested are applied to the
high-speed data probe. The data probe (A3) discriminates whether the input TTL level
is high
or low or bad (middle level). If the input level
i s
high it is detected by if it
is
low it is de-
tected by The input signal is converted to a pair of two-line differential (complementary)
ECL signals and sent to the main assembly. At the input to the main assembly the data signal
is converted from a pair of two-line (differential) ECL signals to a pair of signals at TTL level.
8-84. The pair of data signals at pins 6 and 12 of (A and are applied to the data latch,
If the data input signal i s a high level or a low level i t is clocked out of the data latch on
pin 5. If it i s a bad (middle) level signal the previous level signal i s clocked out of the data
latch. (A bad level appears as tow lows at the and K inputs.)
8-85. In the main assembly the data signals at the junction of R37 and are applied to
a logic level detector. The detector responds to the combined TTL level (or pulses) of the
input signal, and it controls the indication of the logic level indicator lamp, in the data
probe. The two data signals are applied to the data latch, Data from is applied to
an gate. is the input of the pseudo-random word generator.