Rev. 1.20
148
November 20, 2019
Rev. 1.20
149
November 20, 2019
HT66F2740
12V High Current Flash MCU
HT66F2740
12V High Current Flash MCU
Receiving Data
When the UART receiver is receiving data, the data is serially shifted in on the external RX input
pin, LSB first. In the read mode, the UTXR_RXR register forms a buffer between the internal bus
and the receiver shift register. The UTXR_RXR register is a two byte deep FIFO data buffer, where
two bytes can be held in the FIFO while a third byte can continue to be received. Note that the
application program must ensure that the data is read from UTXR_RXR before the third byte has
been completely shifted in, otherwise this third byte will be discarded and an overrun error UOERR
will be subsequently indicated. The steps to initiate a data transfer can be summarized as follows:
•
Make the correct selection of UBNO, UPRT and UPREN bits to define the word length, parity type.
• Setup the UBRG register to select the desired baud rate.
• Set the URXEN bit to ensure that the RX pin is used as a UART receiver pin.
At this point the receiver will be enabled which will begin to look for a start bit.
When a character is received the following sequence of events will occur:
• The URXIF bit in the UUSR register will be set when the UTXR_RXR register has data
available. There will be at most one more character available before an overrun error occurs.
• When the contents of the shift register have been transferred to the UTXR_RXR register, then if
the URIE bit is set, an interrupt will be generated.
• If during reception, a frame error, noise error, parity error, or an overrun error has been detected,
then the error flags can be set.
The URXIF bit can be cleared using the following software sequence:
1. A UUSR register access
2. A UTXR_RXR register read execution
Receive Break
Any break character received by the UART will be managed as a framing error. The receiver
will count and expect a certain number of bit times as specified by the values programmed into
the UBNO bit plus one stop bit. If the break is much longer than 13 bit times, the reception will
be considered as complete after the number of bit times specified by UBNO plus one stop bit.
The URXIF bit is set, UFERR is set, zeros are loaded into the receive data register, interrupts are
generated if appropriate and the URIDLE bit is set. A break is regarded as a character that contains
only zeros with the UFERR flag set. If a long break signal has been detected, the receiver will regard
it as a data frame including a start bit, data bits and the invalid stop bit and the UFERR flag will be
set. The receiver must wait for a valid stop bit before looking for the next start bit. The receiver will
not make the assumption that the break condition on the line is the next start bit. The break character
will be loaded into the buffer and no further data will be received until stop bits are received. It
should be noted that the URIDLE read only flag will go high when the stop bits have not yet been
received. The reception of a break character on the UART registers will result in the following:
•
The framing error flag, UFERR, will be set.
• The receive data register, UTXR_RXR, will be cleared.
•
The UOERR, UNF, UPERR, URIDLE or URXIF flags will possibly be set.
Idle Status
When the receiver is reading data, which means it will be in between the detection of a start bit and the
reading of a stop bit, the receiver status flag in the UUSR register, otherwise known as the URIDLE
flag, will have a zero value. In between the reception of a stop bit and the detection of the next start
bit, the URIDLE flag will have a high value, which indicates the receiver is in an idle condition.