AN-6130PCIe
HOLT INTEGRATED CIRCUITS
26
Appendix – A CPLD Verilog Source
A current copy of this source file is included in the Verilog source file on the CD-ROM.
// Holt PCI_6130 interface
module count_osc (rstn, osc_clk, LED, clk, // clk and reset pins
testpoint,
// test output
add, decoderOutput,
// address decoder
lclk,blast,blast_q,ads,lwr,RDn,WRn,
// Read Write stobes
LEDRD, LEDWR,
// LED flashers
Latch,
// 16 latched outputs
DataBus,
// Data bus In/Out (16)
InputBuffer,
// Inputs (16)
nLINTi,
// Interrupt output pin
Latch2,
TP13
);
// Misc. Signals
input rstn ;
output osc_clk ;
output [7:0]LED ;
output clk ;
output testpoint ;
// Test OE
output TP13;
// Test ADSn
// Inputs
input lclk;
// LCLK 50 MHZ input
input blast;
// blast input
input [5:0]add;
// inputs LA31-LA26 (6) for decoder
input [15:0]InputBuffer;
// 16 status input pins
input ads;
// ADS input
input lwr;
// LW/R input
//input RT1MC8n, RT2MC8n, IRQn;
// Interrupt inputs
// InOuts
inout [15:0]DataBus;
// 16 In/out Data Bus pins
// Outputs
output blast_q;
// blast output
output [4:0]decoderOutput;
// address decoder outputs
output reg RDn;
// /RD output strobe
output reg WRn;
// /WR output strobe
output reg LEDRD, LEDWR;
// LED flashers for 6130 indication
output reg [15:0]Latch;
// 16 latched outputs
output reg [15:0]Latch2;
// 2nd set of latches
output nLINTi;
// Interrupt output to PLX
// Wires
// Constants
`define H6130
8'b11111110
// HI6130 address decode address
`define LatchAddress 8'b11111101
// Latches output decode address
`define InputsAddress 8'b11111011
// Inputs address decode address
`define Latch2Address 8'b11110111
// Inputs address decode address
// Registers
reg
[26:0]c_delay ;
reg
[7:0] add_L;
reg
[0:0] blastq;
reg
[3:0] counter;
reg
[3:0] counter2;
reg
oe;
// output enable for buffer reads
reg
[15:0] mux;
// internal bus for muxing readback bus'
