background image

A

A

B

B

C

C

D

D

E

E

4

4

3

3

2

2

1

1

Provisonal - Female header

CT2196LPST-ND

DIP SWITCHES

JTAG

GND

(rstn)

8

1

2

Default: SW2 position 6 (AUTOEN)
should be Open (UP).

LD0

LD2

LD1

LD3

LD4
LD5

LD6
LD7

LD8
LD9

LD10
LD11

LD12
LD13

LD14
LD15

AUTOEN

SW1
SW2

3V3

T0

T1

T2

T3

T4

T5

T6

T7

T7
T6
T5
T4
T3
T2
T1
T0

3V3

3V3

AUTOEN

SW5

SW4

SW3

SW2

SW1

SW3
SW4

SW5

3V3

3V3

3V3

LD[15:0] {3,5}

ACTIVE

{5}

MTPKTRDY

{5}

nWAIT

{5}

RT1MC8n

{5}

RT2MC8n

{5}

IRQn

{5}

AUTOEN

{5}

READY

{5}

3V3 {5,6}

LCLK {3}

PCIE12VCC

{2}

Title

Size

Document Number

R e v

Date:

Sheet

o f

A

HI-6130 Status Inputs, JTAG

Holt Integrated Circuits

23351 Madero, Mission Viejo, CA 92691

B

4

7

Thursday, September 19, 2013

www.holtic.com

Title

Size

Document Number

R e v

Date:

Sheet

o f

A

HI-6130 Status Inputs, JTAG

Holt Integrated Circuits

23351 Madero, Mission Viejo, CA 92691

B

4

7

Thursday, September 19, 2013

www.holtic.com

Title

Size

Document Number

R e v

Date:

Sheet

o f

A

HI-6130 Status Inputs, JTAG

Holt Integrated Circuits

23351 Madero, Mission Viejo, CA 92691

B

4

7

Thursday, September 19, 2013

www.holtic.com

J15

header_1x2Male pins

1

1

2

2

J14

header_1x2Male pins

1

1

2

2

pad

1

TP30

VCCIO0

VCCIO1

I/Os in Bank 0
for XO1200

I/Os in Bank 1
for XO2280

Pin name sequence
PT(640,1200,2280)

U8A

LCMXO640/1200/2280-FT256/FTN256

NC/PT2A/PT2C

B2

NC/PT2B/PT2D

B3

PT2A/PT3A/PT3A

A2

PT2B/PT3B/PT3B

A3

NC/PT2C/PT3C

D3

NC/PT2D/PT3D

D4

PT2F/PT4B/PT4B

C5

PT2E/PT4A/PT4A

C4

PT2C/PT3C/PT5A

D6

PT2D/PT3D/PT5B

D5

PT3A/PT3E/PT5C

B4

PT3B/PT3F/PT5D

B5

NC/PT4D/PT6F

E6

NC/PT4C/PT6E

E7

PT3F/PT5B/PT6D

A4

PT3E/PT5A/PT6C

A5

PT3C/PT5C/PT6A

C6

PT3D/PT5D/PT6B

C7

PT4A/PT5E/PT7A

B6

PT4B/PT5F/PT7B

B7

PT4C/PT6A/PT7C

A6

PT4D/PT6B/PT7D

A7

PT4E/PT6C/PT8C

B8

PT4F/PT6D/PT8D

C8

PT5B/PT6F/PT9B/CLK0

D7

PT5A/PT6E/PT9A

D8

PT9A/PT7A/PT9C

E8

PT9B/PT7B/PT9D

E9

PT6B/PT7D/PT10B/CLK1

A9

PT6A/PT7C/PT10A

A10

PT6C/PT7E/PT10C

C9

PT6D/PT7F/PT10D

C10

PT8C/PT8A/PT10E

D9

PT8D/PT8B/PT10F

D10

PT5C/PT8C/PT11A

B9

PT5D/PT8D/PT11B

B10

PT7C/PT8E/PT12A

A11

PT7D/PT8F/PT12B

A12

PT7A/PT9A/PT12C

B11

PT7B/PT9B/PT12D

B12

PT8A/PT9C/PT13C

C11

PT8B/PT9D/PT13D

C12

PT7F/PT9F/PT14B

A14

PT7E/PT9E/PT14A

A13

PT9C/PT10A/PT14C

D11

PT9D/PT10B/PT14D

D12

NC/PT10C/PT15A

E10

NC/PT10D/PT15B

E11

PT9E/PT10E/PT15C

B13

PT9F/PT10F/PT15D

C13

NC/PT11A/PT16A

B14

NC/PT11B/PT16B

C14

NC/PT11C/PT16C

A15

NC/PT11D/PT16D

B15

J2

header_1x8 Male pins

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

FB5

1

2

R57

10K

1

2

J3

HEADER 10

1

2

3

4

5

6

7

8

9

10

3

2

1

4

5

6

ON

 (C

LO

SED)

SW2

SMD 6-POS DIP Switch

pad

1

VCCIO5

VCCIO4

I/Os in Bank 5
for XO1200

I/Os in Bank 4
for XO2280

Pin name sequence
PB(640,1200,2280)

U8C

LCMXO640/1200/2280-FT256/FTN256

NC/PB2B/PB2B

P3

NC/PB2D/PB2D

N6

NC/PB2C/PB2C

N5

PB2A/PB3A/PB3A

T2

PB2B/PB3B/PB3B

T3

PB2C/PB3C/PB3C

R4

PB3D/PB4D/PB4D

T4

PB3A/PB4A/PB4A

P5

PB3B/PB4B/PB4B

P6

PB3C/PB4C/PB4C

T5

PB4A/PB5A/PB5A

R6

PB2D/PB3D/PB3D

R5

PB4B/PB5B/PB5B

T6

PB4C/PB5C/PB6A

T8

PB4D/PB5D/PB6B

T7

NC/PB6A/PB7C

M7

NC/PB6B/PB7D

M8

PB4E/PB6C/PB8C

R7

PB4F/PB6D/PB8D

R8

PB5C/PB6E/PB9A

P7

PB5D/PB6F

/PB9B

P8

PB5B/PB7B/PB10F/CLK2

N9

PB5A/PB7A/PB10E

N8

PB7A/PB7C/PB10C

P9

PB7B/PB7D/PB10D

P10

PB6B/PB7F/PB10B/CLK3

M9

PB6A/PB7E/PB10A

M10

PB6C/PB8A/PB11C

R9

PB6D/PB8B/PB11D

R10

PB7C/PB8C/PB12A

T10

PB7D/PB8D/PB12B

T11

NC/PB8E/PB12C

N10

NC/PB8F/PB12D

N11

PB7E/PB9A/PB13A

R11

PB7F/PB9B/PB13B

R12

PB8A/PB9C/PB13C

P11

PB8B/PB9D/PB13D

P12

PB8C/PB9E/PB14A

T13

PB8D/PB9F/PB14B

T12

PB9A/PB10A/PB14C

R13

PB9B/PB10B/PB14D

R14

PB9C/PB10C/PB15A

T14

PB9D/PB10D/PB15B

T15

NC/PB11A/PB16A

R15

NC/PB11B/PB16B

R16

SLEEPN

P13

PB9F/PB10F/PB15D

P14

NC/PB11C/PB16C

P15

NC/PB11D/PB16D

P16

TDI

N7

TDO

M6

TMS

P4

TCK

R3

NC/PB2A/PB2A

P2

J12

HEADER 10

1

2

3

4

5

6

7

8

9

10

pad

1

FB4

1

2

Содержание AN-6130PCIe MIL-STD 1553

Страница 1: ...16 PCI Express PCIe 1 1 slot on a PC running Windows 7 The HI 6130 is a single supply 3 3V rail BC MT RT1 RT2 Multi Terminal device for MIL STD 1553 dual redundant bus communications The card is bundl...

Страница 2: ...documentation and software Topics Introduction Quick Start Guide Hardware Programming Reference Software Customization Summary Schematics and BOM Board Default Setup Set SW2 position 6 set to Off up p...

Страница 3: ...ns 1 5 are user defined These may be used by the demo program in future releases Default DIP switch settings Metal brackets are provided for both full height and low profile PCIe cards Use the correct...

Страница 4: ...in the HI 6130 The MSB bit 15 high indicates the HI 6130 READY is high which means the device is ready for the host to access the memory and registers in the device See the HI 6130 data sheet for more...

Страница 5: ...ke it accessible to the scope probe If no external RT or test equipment is connected to the bus then use a 70 ohm termination resistor on the cable output or the signal will be distorted when viewed w...

Страница 6: ...l Bus bridge and provides the interface between the PCIe slot and the local bus LB A CPLD translates the LB signals into CSn RDn and WRn strobe signals for the HI 6130 timings The CPLD also provides o...

Страница 7: ...tion 4 PLX Debug Utilities Holt uses this utility to program the two EEPROMs The HI 6130 uses a 16 bit data bus 16 bit address bus and three more lines to select the device during reads and writes The...

Страница 8: ...sions D1 ACKIRQ HI 6130 input D2 TP31 CPLD spare pin D3 RAMEDC HI 6130 Error detection correction input Set Low for this program D4 TXINHB HI 6130 Bus B inhibit input D5 TXINHA HI 6130 Bus A inhibit i...

Страница 9: ...ved D6 IRQ 6130 HI 6130 interrupt output D7 N A Not defined D8 AUTOEN Set by the SW2 DIP switch 6 Input to HI 6130 for auto initialization from EEPROM D9 D5 Not used by connected to a pad on the PCB f...

Страница 10: ...n signal is used by the CPLD to time when to de assert the CSn RWn or WRn signals to the HI 6130 and the internal latches and input buffers The ADSn signal from the LB is used by the CPLD to start the...

Страница 11: ...AN 6130PCIe HOLT INTEGRATED CIRCUITS 11 CPLD Functional Block Diagram...

Страница 12: ...R TRANSCEIVER POWER TEST MODE RT2SSF ACKIRQ RT1SSF MR RT2A4 0 AUTOEN RT2AP EECOPY BENDI RAMEDC RT1LOCK MTTCLK RT1A4 0 RT1AP MTSTOFF RT2LOCK RT1ENA RT2ENA BCENA MTENA Host Bus Interface HI 6130 Only IR...

Страница 13: ...HI6130 c with accompanying header file HI6130 h To rebuild these projects the following three items are needed Holt demo projects contained on the CD ROM Microsoft Visual Studio 2012 Not Provided PLX...

Страница 14: ...double click on the PCIe6130Test project file in the PCIe6130 test project folder 1 The Solution Explorer with the source files is shown on the left side If this is not seen then open the Solution Exp...

Страница 15: ...led when the SDK is installed PLX PEX8311 RDK Hardware Reference Manual and the PLX PEX8311 data book Latest versions are available from the PLX website These are not included in the SDK Holt HI 6130...

Страница 16: ...PLX API to access the LB with either PlxPci_PciBarSpaceRead or PlxPci_PciBarSpaceWrite One of the input parameters to these API s is bOffsetAsLocalAddr this parameter controls how the API uses the U32...

Страница 17: ...RATED CIRCUITS 17 Select the Holt PCIe card from the Command menu or press the green icon button on the left and select the device with Dev ID 9056 and Ven ID 10B5 The PEX8311 consists internally of a...

Страница 18: ...SIG obtained by becoming a PCI SIG member or a sub ID obtained from PLX For detailed information on these parameters and the PLX API s refer to the PLX SDK user s guide and data sheet on the PEX8311 F...

Страница 19: ...s It s a good idea to review these two projects when first becoming familiar with the PLX API s These PLX projects do not run on the Holt PCIe card because the LB memory spaces are defined differently...

Страница 20: ...ED CIRCUITS 20 The main menu will appear below Press D to display the HI 6130 system registers with labels followed by the same registers values formatted by beginning and end addressed rows followed...

Страница 21: ...ring the message To view the messages on a scope trigger on the rising edge of this signal with one probe and view the bus signal on another probe at the ABUS test point This waveform shows no RT resp...

Страница 22: ...ansmit occurs on a different bus stub RT1 Demo If an external RT is not immediately available on chip RT1 can be enabled in the HI 6130 by entering command B The waveform below shows the HI 6130 RT1 r...

Страница 23: ...Codes using the Holt API library Optionally use the internal BC to transmit messages to the RT using the BC Major Minor frame demo N The bus connector should be terminated with 75 ohms or connected to...

Страница 24: ...AN 6130PCIe HOLT INTEGRATED CIRCUITS 24 Console main menu and HI 6130 registers SRT enabled showing message traffic received using B command and N command...

Страница 25: ...AN 6130PCIe HOLT INTEGRATED CIRCUITS 25 SRT showing Mode Codes received transmitted from an external BC...

Страница 26: ...ffer 16 status input pins input ads ADS input input lwr LW R input input RT1MC8n RT2MC8n IRQn Interrupt inputs InOuts inout 15 0 DataBus 16 In out Data Bus pins Outputs output blast_q blast output out...

Страница 27: ...01111 led5 Spare CS default add_L 8 b11111111 defaul all OFF endcase 16 bit 3 to 1 multiplexer always begin case add_L LatchAddress mux Latch First latches routed to mux InputsAddress mux InputBuffer...

Страница 28: ...counter2 3 LEDWR 1 b1 turn off led else counter2 counter2 1 end Latched 16 GPIO s For Latch outputs always posedge WRn or negedge rstn begin if rstn Latch 16 b0001000000110000 Defaults LED1 On low TXI...

Страница 29: ...assign DataBus oe mux 16 hZ Read the 16 inputs Misc Logic Interrupt MR assign nLINTi InputBuffer 4 InputBuffer 5 InputBuffer 6 Interrupt pins End of Misc The c_delay counter is used to slow down the...

Страница 30: ...same hardware and software techniques would apply The devices that have a parallel interface would be the easiest to interface on the LB Some suggested ARINC 429 16 bit parallel parts are the HI 3582...

Страница 31: ...the HI 6130 but does have some differences in the registers and pin outs The HI 6120 is simpler to use and cost less than the HI 6130 This change would require a revised board design not an add on bo...

Страница 32: ...the same clock to generate the synchronized strobe signals internal to the CPLD and the CSn RDn and WRn strobe signals to the HI 6130 For a faster LB use up to 66MHz for the LB clock input of the PEX8...

Страница 33: ...elopment Some guidance how to enhance and customize the design with additional MIL STD terminals ARINC 429 protocol IC s Discrete to Digital devices and memory was provided For questions regarding thi...

Страница 34: ...CMX1200C3FTN245I 17 x 17 mm Address decoder Chip Selects RD WR Strobes 6130 RD WR Access LED indicators Status and DIP SW inputs Date Changes 9 19 2013 Rev A 12V 12V to 5V DC DC 3V3 HI 6130 PEX8311 Ti...

Страница 35: ...0 B14 PETn0 B15 GND B16 PRSNT2 B17 GND B18 PRSNT1 A1 12V A2 12V A3 GND A4 JTAG2 A5 JTAG3 A6 JTAG4 A7 JTAG5 A8 3 3V A9 3 3V A10 PERST A11 GND A12 REFCLK A13 REFCLK A14 GND A15 PERp0 A16 PERn0 A17 GND A...

Страница 36: ...61 0 01uF C73 0 01uF U7 LT1963AEST 2 5 VIN 1 GND 2 VOUT 3 RN11 742 08 3 103 J XX 1 2 3 4 5 6 7 8 C53 4 7uF 10V C50 0 1uF C74 0 1uF RN13 742 08 3 103 J XX 1 2 3 4 5 6 7 8 LED7 LED C62 0 1uF C71 0 01uF...

Страница 37: ...E PT9A D8 PT9A PT7A PT9C E8 PT9B PT7B PT9D E9 PT6B PT7D PT10B CLK1 A9 PT6A PT7C PT10A A10 PT6C PT7E PT10C C9 PT6D PT7F PT10D C10 PT8C PT8A PT10E D9 PT8D PT8B PT10F D10 PT5C PT8C PT11A B9 PT5D PT8D PT1...

Страница 38: ...0K 1 2 JP6 Solder Jumper TP13 C86 4 7uF 10V R64 330 1 2 R68 330 1 2 TP11 TP31 Sp L C97 10uF 16V LED8 LED C94 100nF C98 0 1uF pad 1 TP12 OSC2 50 0MHz OE 1 GD 2 OUT 3 VCC 4 LED11 LED C87 100nF C95 100nF...

Страница 39: ...5 0 1uF 1 2 FB2 1 2 1 2 C110 01uF 1 2 C103 0 1uF 1 2 C113 4u7 10V 1 2 C106 0 1uF 1 2 C101 0 1uF 1 2 C107 0 1uF 1 2 C108 0 1uF 1 2 FB3 1 2 C112 0 1uF 1 2 VCCIO2 VCCIO3 Pin name sequence PR 640 1200 228...

Страница 40: ...e Document Number Rev Date Sheet o f Doc PEX 8311 NC BALLS A 7 7 Tuesday August 13 2013 23351 Madero Mission Viejo CA 92691 www holtic com Holt Integrated Circuits U1B PEX83111 N C T1 N C P1 N C W6 N...

Страница 41: ...Viejo CA 92691 A 1 1 www holtic com Title Size Document Number Rev Date Sheet o f NEW HI 6130 PCIe MIL STD 1553 Cable Holt Integrated Circuits 23351 Madero Mission Viejo CA 92691 A 1 1 www holtic com...

Страница 42: ...1 Resistor 10K Ohm 5 1 10W 0603 R4 R5 R12 R21 R22 R26 R27 R39 R40 R43 R44 R 45 R46 R48 R49 R51 R57 R63 R65 R72 R133 P10KGCT ND Panasonic ERJ 3GEYJ103V 29 4 Header 1x3 Male 0 1 Pitch JP2 JP3 JP4 JP5 S1...

Страница 43: ...EVISION HISTORY P N Rev Date Description of Change AN 6130PCIe NEW 09 27 2013 Release AN 6130PCIe A 06 30 2014 Revise for API demo program changes AN 6130PCIe B 03 04 2015 Update board photo on page 1...

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