AN-6130PCIe
HOLT INTEGRATED CIRCUITS
27
// Get IC clk and reset
GSR GSR_INST (.GSR(rstn));
// Reset occurs when argument is active low.
OSCC OSCC_1 (.OSC(osc_clk)) ;
// Logic
assign LED[3:0] = add_L;
// copy decoder outputs to LEDs for test
assign LED[4] = blast_q;
// copy of blast output
assign LED[5] = WRn;
// copy WRn to output
assign LED[6] = RDn;
// copy WRn to output
assign LED[7] = lclk;
// copy clock to output
// End of test
assign decoderOutput = add_L;
assign TP13 = ads;
/* 3-8 Address Decoders */
always@(*)
case (add)
6'b001000 : add_L = `H6130;
// led1 CS20 - 6130
6'b001001 : add_L = `LatchAddress;
// led2 CS24 - Output latches
6'b001010 : add_L = `InputsAddress;
// led3 CS28 - Inputs
6'b001011 : add_L = `Latch2Address;
// led4 CS2C - Latch2 output latches
6'b001100 : add_L = 8'b11101111;
// led5 Spare CS
default : add_L = 8'b11111111;
// defaul all OFF
endcase
/* 16 bit 3 to 1 multiplexer */
always@(*)
begin
case(add_L)
`LatchAddress : mux = Latch;
// First latches routed to mux
`InputsAddress : mux = InputBuffer;
// Status inputs (6130) routed to mux
`Latch2Address : mux = Latch2;
//Second set of latches routed to mux
default : mux = 16'hFFFF;
// default
endcase
end
/* RD, RW, 6130CS Stobe generation */
// generate delayed blast signal used to clear RD, WR.
always @(posedge lclk)
begin
if (blast)
blastq <= 1'b1;
// set high during reset
else
blastq <= 1'b0;
// set high during reset
end
assign blast_q = blastq;
// leave as output pin for possible debugging later
// generate bracketed RDn stobe
always @(posedge lclk or negedge blastq)
begin
if(~blastq)
RDn <= 1'b1;
// set rd high
else begin
if(~lwr && ~ads)
RDn <= 1'b0;
// set rd low
end
end
// generate bracketed WRn stobe
always @(posedge lclk or negedge blastq)
begin
if (~blastq)
WRn <= 1'b1 ;
// set wr high if blast_q =0
else begin
