Hitachi 149
Figure 7.15 indicates an example of the basic cycle. Because a slower synchronous DRAM is
connected, setting the WCR and MCR bits can extend the cycle. The number of cycles from the
ACTV command output cycle Tr to the READA command output cycle Tc can be specified by the
RCD bit of the MCR. 0 specifies 1 cycle; 1 specifies 2 cycles. For 2 cycles, a NOP command issue
cycle Trw for the synchronous DRAM is inserted between the Tr cycle and the Tc cycle. The
number of cycles between the READA command output cycle Tc and the initial read data fetch
cycle Td1 can be specified independently for areas CS2 and CS3 between 1 cycle and 4 cycles
using the W21/W20 and W31/W30 bits of the WCR. The CAS latency when using bus arbitration
in the partial-share master mode can be set differently for CS2 and CS3 spaces. The number of
cycles at this time corresponds to the number of CAS latency cycles of the synchronous DRAM.
When 2 cycles or more, a NOP command issue cycle Tw is inserted between the Tc cycle and the
Td1 cycle. The number of cycles in the precharge completion waiting cycle Tap is specified by the
TRP bit of the MCR. When the CAS latency is 1, a Tap cycle of 1 or 2 cycles is generated. When
the CAS latency is 2 or more, a Tap cycle equal to the TRP specification – 1 is generated. During
the Tap cycle, no commands other than NOP are issued to the same bank. Figure 7.16 shows an
example of burst read timing when RCD is 1, W31/W30 is 01, and TRP is 1.
With the synchronous DRAM cycle, when the bus cycle starts in the ordinary space access, the BS
signal asserted for 1 cycle is asserted in each of cycles Td1–Td4 for the purpose of the external
address monitoring described in the section on bus arbitration. When another CS space is accessed
after an synchronous DRAM read with a wait between buses specification of 0, the BS signal may
be continuously asserted. The address is updated every time data is fetched while burst reads are
being performed. The burst transfer unit is 16 bytes, so address updating affects A3–A1. The
access order follows address order in 16-byte data transfers by the DMAC, but reading starts from
the a 4 so that the last missed data in the fill operation after a cache miss can be read.
When the data width is 16 bits, 8 burst cycles are required for a 16-byte data transfer. The data
fetch cycle goes from Td1 to Td8. From Td1 to Td8, the BS signal is asserted in every cycle.
Synchronous DRAM CAS latency is up to 3 cycles, but the CAS latency of the bus state controller
can be specified up to 4. This is so that circuits containing latches can be installed between
synchronous DRAMs and the SH7095.
Содержание SH7095
Страница 1: ...SH7095 Hardware User Manual ...
Страница 16: ...Hitachi 5 1 2 Block Diagram Figure 1 1 is a block diagram of the SH7095 Figure 1 1 Block Diagram ...
Страница 23: ...12 Hitachi ...
Страница 63: ...52 Hitachi ...
Страница 77: ...66 Hitachi ...
Страница 105: ...94 Hitachi Figure 5 14 Pipeline Operation when Interrupts are Enabled by Changing the SR ...
Страница 127: ...116 Hitachi ...
Страница 152: ...Hitachi 141 Figure 7 8 Example of 32 Bit Data Width SRAM Connection ...
Страница 157: ...146 Hitachi Figure 7 13 Synchronous DRAM 32 bit Device Connection ...
Страница 161: ...150 Hitachi Figure 7 15 Basic Burst Read Timing Auto Precharge ...
Страница 167: ...156 Hitachi Figure 7 20 Burst Read Timing Bank Active Same Row Address ...
Страница 168: ...Hitachi 157 Figure 7 21 Burst Read Timing Bank Active Different Row Addresses ...
Страница 169: ...158 Hitachi Figure 7 22 Write Timing No Precharge ...
Страница 170: ...Hitachi 159 Figure 7 23 Write Timing Bank Active Same Row Address ...
Страница 178: ...Hitachi 167 a Phase Shifted 90 by PLL b Phase Shift Using PLL is 0 Figure 7 28 Phase Shift with the PLL ...
Страница 180: ...Hitachi 169 Figure 7 29 Example of a DRAM Connection 32 Bit Data Width ...
Страница 190: ...Hitachi 179 Figure 7 36 Example of Pseudo SRAM Connection 1 M pseudo SRAM ...
Страница 191: ...180 Hitachi Figure 7 37 Example of Pseudo SRAM Connection 4 M pseudo SRAM ...
Страница 209: ...198 Hitachi Figure 7 50 Master and Partial Share Master Connections ...
Страница 218: ...Hitachi 207 EX Instruction execution MA Memory Access WB Write back Figure 8 3 Reading during a Cache Hit ...
Страница 231: ...220 Hitachi ...
Страница 287: ...276 Hitachi ...
Страница 307: ...296 Hitachi Note For a CPU writing H AA55 to FRC Figure 11 2 FRC Access Operation Write ...
Страница 308: ...Hitachi 297 Note For an FRC reading from a CPU H AA55 Figure 11 3 FRC Access Operation Read ...
Страница 333: ...322 Hitachi ...
Страница 370: ...Hitachi 359 Figure 13 12 Sample Flowchart for Receiving Multiprocessor Serial Data ...
Страница 371: ...360 Hitachi Figure 13 12 Sample Flowchart for Receiving Multiprocessor Serial Data cont ...
Страница 395: ...384 Hitachi ...
Страница 402: ...Hitachi 391 Figure 15 6 PLL Synchronization Settling Timing ...
Страница 405: ...394 Hitachi Figure 15 7 Reset Input Timing Figure 15 8 Interrupt Signal Input Timing With PLL1 Off ...
Страница 408: ...Hitachi 397 Figure 15 13 Bus Release Timing Slave Mode With PLL1 Off ...
Страница 436: ...Hitachi 425 Figure 15 33 Synchronous DRAM Mode Register Write Cycle TRP 1 Cycle ...
Страница 437: ...426 Hitachi Figure 15 34 Synchronous DRAM Mode Register Write Cycle TRP 2 Cycles ...
Страница 439: ...428 Hitachi Figure 15 36 Synchronous DRAM Auto Refresh Cycle Shown From Precharge Cycle TRP 1 Cycle TRAS 2 Cycles ...
Страница 449: ...438 Hitachi Figure 15 46 DRAM CAS Before RAS Refresh Cycle TRP 1 Cycle TRAS 2 Cycles PLL On ...
Страница 454: ...Hitachi 443 Figure 15 51 DRAM CAS Before RAS Refresh Cycle TRP 1 Cycle TRAS 2 Cycles PLL Off ...
Страница 461: ...450 Hitachi Figure 15 58 Pseudo SRAM Auto Refresh Cycle PLL On TRP 1 Cycle TRAS 2 Cycles ...
Страница 462: ...Hitachi 451 Figure 15 59 Pseudo SRAM Self Refresh Cycle PLL On TRP 1 Cycle TRAS 2 Cycles ...
Страница 467: ...456 Hitachi Figure 15 64 Pseudo SRAM Auto Refresh Cycle PLL Off TRP 1 Cycle TRAS 2 Cycles ...
Страница 468: ...Hitachi 457 Figure 15 65 Pseudo SRAM Self Refresh Cycle PLL Off TRP 1 Cycle TRAS 2 Cycles ...
Страница 471: ...460 Hitachi Figure 15 68 Interrupt Vector Fetch Cycle PLL On No Waits ...
Страница 472: ...Hitachi 461 Figure 15 69 Interrupt Vector Fetch Cycle PLL Off No Waits ...
Страница 473: ...462 Hitachi Figure 15 70 Interrupt Vector Fetch Cycle 1 External Wait Cycle ...
Страница 474: ...Hitachi 463 Figure 15 71 Address Monitor Cycle ...
Страница 490: ...Hitachi 479 B 2 Register Chart ...