132 Hitachi
•
Bit 9—RAS Down Mode (RASD): Bank active mode.
Bit 9 (RASD)
Description
0
For synchronous DRAM, read or write is performed using auto-
precharge mode
.
The next access always starts with bank active
commands.
1
For synchronous DRAM, access ends with bank active status. This is
only valid for area 3. When area 2 is synchronous DRAM, the mode is
always auto precharge.
•
Bits 7, 5, and 4—Address Multiplex (AMX2–AMX0): For DRAM interface:
Bit 7
(AMX2)
Bit 5
(AMX1)
Bit 4
(AMX0)
Description
0
0
0
8-bit column address DRAM
1
9-bit column address DRAM
1
0
10-bit column address DRAM
1
11-bit column address DRAM
1
0
0
Reserved (do not set)
1
Reserved (do not set)
1
0
Reserved (do not set)
1
Reserved (do not set)
For synchronous DRAM interface:
Bit 7
(AMX2)
Bit 5
(AMX1)
Bit 4
(AMX0)
Description
0
0
0
16-Mbit DRAM (1M
×
16 bits)
1
16-Mbit DRAM (2M
×
8 bits)*
1
0
16-Mbit DRAM (4M
×
4 bits)*
1
4-Mbit DRAM (256k
×
16 bits)
1
0
0
Reserved (do not set)
1
Reserved (do not set)
1
0
Reserved (do not set)
1
2-Mbit DRAM (128k
×
16 bits)
Note:
Reserved. Do not set when SZ bit in MCR is 0 (16-bit bus width).
Содержание SH7095
Страница 1: ...SH7095 Hardware User Manual ...
Страница 16: ...Hitachi 5 1 2 Block Diagram Figure 1 1 is a block diagram of the SH7095 Figure 1 1 Block Diagram ...
Страница 23: ...12 Hitachi ...
Страница 63: ...52 Hitachi ...
Страница 77: ...66 Hitachi ...
Страница 105: ...94 Hitachi Figure 5 14 Pipeline Operation when Interrupts are Enabled by Changing the SR ...
Страница 127: ...116 Hitachi ...
Страница 152: ...Hitachi 141 Figure 7 8 Example of 32 Bit Data Width SRAM Connection ...
Страница 157: ...146 Hitachi Figure 7 13 Synchronous DRAM 32 bit Device Connection ...
Страница 161: ...150 Hitachi Figure 7 15 Basic Burst Read Timing Auto Precharge ...
Страница 167: ...156 Hitachi Figure 7 20 Burst Read Timing Bank Active Same Row Address ...
Страница 168: ...Hitachi 157 Figure 7 21 Burst Read Timing Bank Active Different Row Addresses ...
Страница 169: ...158 Hitachi Figure 7 22 Write Timing No Precharge ...
Страница 170: ...Hitachi 159 Figure 7 23 Write Timing Bank Active Same Row Address ...
Страница 178: ...Hitachi 167 a Phase Shifted 90 by PLL b Phase Shift Using PLL is 0 Figure 7 28 Phase Shift with the PLL ...
Страница 180: ...Hitachi 169 Figure 7 29 Example of a DRAM Connection 32 Bit Data Width ...
Страница 190: ...Hitachi 179 Figure 7 36 Example of Pseudo SRAM Connection 1 M pseudo SRAM ...
Страница 191: ...180 Hitachi Figure 7 37 Example of Pseudo SRAM Connection 4 M pseudo SRAM ...
Страница 209: ...198 Hitachi Figure 7 50 Master and Partial Share Master Connections ...
Страница 218: ...Hitachi 207 EX Instruction execution MA Memory Access WB Write back Figure 8 3 Reading during a Cache Hit ...
Страница 231: ...220 Hitachi ...
Страница 287: ...276 Hitachi ...
Страница 307: ...296 Hitachi Note For a CPU writing H AA55 to FRC Figure 11 2 FRC Access Operation Write ...
Страница 308: ...Hitachi 297 Note For an FRC reading from a CPU H AA55 Figure 11 3 FRC Access Operation Read ...
Страница 333: ...322 Hitachi ...
Страница 370: ...Hitachi 359 Figure 13 12 Sample Flowchart for Receiving Multiprocessor Serial Data ...
Страница 371: ...360 Hitachi Figure 13 12 Sample Flowchart for Receiving Multiprocessor Serial Data cont ...
Страница 395: ...384 Hitachi ...
Страница 402: ...Hitachi 391 Figure 15 6 PLL Synchronization Settling Timing ...
Страница 405: ...394 Hitachi Figure 15 7 Reset Input Timing Figure 15 8 Interrupt Signal Input Timing With PLL1 Off ...
Страница 408: ...Hitachi 397 Figure 15 13 Bus Release Timing Slave Mode With PLL1 Off ...
Страница 436: ...Hitachi 425 Figure 15 33 Synchronous DRAM Mode Register Write Cycle TRP 1 Cycle ...
Страница 437: ...426 Hitachi Figure 15 34 Synchronous DRAM Mode Register Write Cycle TRP 2 Cycles ...
Страница 439: ...428 Hitachi Figure 15 36 Synchronous DRAM Auto Refresh Cycle Shown From Precharge Cycle TRP 1 Cycle TRAS 2 Cycles ...
Страница 449: ...438 Hitachi Figure 15 46 DRAM CAS Before RAS Refresh Cycle TRP 1 Cycle TRAS 2 Cycles PLL On ...
Страница 454: ...Hitachi 443 Figure 15 51 DRAM CAS Before RAS Refresh Cycle TRP 1 Cycle TRAS 2 Cycles PLL Off ...
Страница 461: ...450 Hitachi Figure 15 58 Pseudo SRAM Auto Refresh Cycle PLL On TRP 1 Cycle TRAS 2 Cycles ...
Страница 462: ...Hitachi 451 Figure 15 59 Pseudo SRAM Self Refresh Cycle PLL On TRP 1 Cycle TRAS 2 Cycles ...
Страница 467: ...456 Hitachi Figure 15 64 Pseudo SRAM Auto Refresh Cycle PLL Off TRP 1 Cycle TRAS 2 Cycles ...
Страница 468: ...Hitachi 457 Figure 15 65 Pseudo SRAM Self Refresh Cycle PLL Off TRP 1 Cycle TRAS 2 Cycles ...
Страница 471: ...460 Hitachi Figure 15 68 Interrupt Vector Fetch Cycle PLL On No Waits ...
Страница 472: ...Hitachi 461 Figure 15 69 Interrupt Vector Fetch Cycle PLL Off No Waits ...
Страница 473: ...462 Hitachi Figure 15 70 Interrupt Vector Fetch Cycle 1 External Wait Cycle ...
Страница 474: ...Hitachi 463 Figure 15 71 Address Monitor Cycle ...
Страница 490: ...Hitachi 479 B 2 Register Chart ...