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13.2
Input/Output Pins
Table 13-1 shows the SCI3 pin configuration.
Table 13-1 Pin Configuration
Pin Name
Abbrev.
I/O
Function
SCI3 clock
SCK3
I/O
SCI3 clock input/output
SCI3 receive data input
RXD
Input
SCI3 receive data input
SCI3 transmit data output
TXD
Output
SCI3 transmit data output
13.3
Register Descriptions
The SCI3 has the following registers for each channel. For details on register addresses and
register states during each process, refer to appendix B, Internal I/O Register.
•
Receive Shift Register (RSR)
•
Receive Data Register (RDR)
•
Transmit Shift Register (TSR)
•
Transmit Data Register (TDR)
•
Serial Mode Register (SMR)
•
Serial Control Register3 (SCR3)
•
Serial Status Register (SSR)
•
Bit Rate Register (BRR)
Содержание H8/3670F-ZTAT HD64F3670
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