Hitachi H8/3008, Руководство по оборудованию

Страница: 632 / 645

616
Modes 3 and 4: Figure D.2 is a timing diagram for the case in which
RES
goes low during an
external memory access in mode 3 or 4. As soon as
RES
goes low, all ports are initialized to the
input state.
AS
,
RD
,
HWR
,
LWR
, and
CS
0
go high, and D
15
to D
0
go to the high-impedance state.
The address bus is initialized to the low output level 2.5
φ
clock cycles after the low level of
RES
is sampled. However, when PA
4
to PA
6
are used as address bus pins, or when P8
3
to P8
1
and PB
0
to PB
3
are used as CS output pins, they go to the high-impedance state at the same time as
RES
goes low. Clock pin P6
7
/
φ
goes to the output state at the next rise of
φ
after
RES
goes low.
T
1
T
2
T
3
Access to external
memory
H'00000
High impedance
High impedance
AS
,
RD
(read)
D
15
to D
0
(write)
HWR
,
LWR
(write)
Internal reset
signal
RES
P6
7
/
φ
I/O port,
PA
4
/A
23
to PA
6
/A
21
,
CS
7
to
CS
1
CS
0
A
20
to A
0
Figure D.2 Reset during Memory Access (Modes 3 and 4)