Hitachi H8/3008, Руководство по оборудованию

Страница: 449 / 645

433
Table 17.3 Clock Timing (Preliminary)
V
CC
= 3.0 V
to 5.5 V
V
CC
= 5.0 V
± 10%
Item Symbol Min Max Min Max Unit Test Conditions
External clock input low
pulse width t
EXL
30 — 15 — ns Figure 17.6
External clock input high
pulse width t
EXH
30 — 15 — ns
External clock rise time t
EXr
— 8 — 5 ns
External clock fall time t
EXf
— 8 — 5 ns
Clock low pulse width t
CL
0.4 0.6 0.4 0.6 t
cyc
φ ≥
5 MHz Figure
80 — 80 — ns
φ
< 5 MHz
19.17
Clock high pulse width t
CH
0.4 0.6 0.4 0.6 t
cyc
φ ≥
5 MHz
80 — 80 — ns
φ
< 5 MHz
External clock output
settling delay time t
DEXT
* 500 — 500 — µs Figure 17.7
Note: * t
DEXT
includes a
RES
pulse width (t
RESW
). t
RESW
= 20 t
cyc
EXTAL
t
EXr
t
EXf
V
CC
×
0.7
0.3 V
t
EXH
t
EXL
V
CC
×
0.5
Figure 17.6 External Clock Input Timing