269
9.7.7
Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode
(Cascaded Connection)
If an increment pulse occurs in the T
3
state of an 8TCNT byte write cycle in 16-bit count mode,
the counter write takes priority and the byte data for which the write was performed is not
incremented. The byte data for which a write was not performed is incremented. Figure 9.24
shows the timing when an increment pulse occurs in the T
2
state of a byte write to 8TCNT (upper
byte). If an increment pulse occurs in the T
2
state, on the other hand, the increment takes priority.
φ
Address bus
8TCNTH address
Internal write signal
8TCNT input clock
8TCNT (upper byte)
N
N+1
8TCNT write data
T
1
T
3
T
2
8TCNT (upper byte) byte write cycle
8TCNT (lower byte)
X+1
X
Figure 9.24 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode
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