Hitachi C28W40TN, Руководство по обслуживанию

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Test Point Net Name Function
TP154 AV_A8 SDRAM address 8
TP155 AV_A7 SDRAM address 7
TP156 AV_A6 SDARM address 6
TP157 AV_A5 SDRAM address 5
TP158 AV_A4 SDARM address 4
TP159 AV_A3 SDRAM address 3
TP160 AV_A2 SDRAM address 2
TP161 AV_A1 SDRAM address 1
TP162 AV_A0 SDRAM address 0
TP163 AV_A10 SDRAM address 10
TP164 AV_A11 SDRAM address 11
TP165 /BCS1 SDRAM 1 chip select
TP166 /BCS0 SDRAM 0 chip select
TP167 /BRAS RAS SDRAM control
TP168 /BCAS CAS SDRAM control
TP169 /BWE SDRAM write enable
TP170 DQM SDRAM data control mask
TP171 LP2 PLL control
TP174 PLLVDD 81MHz phase lock loop local supply
TP172 PLLVSS 81MHz PLL local ground
TP178 LP2 (via resistor) PLL control
TP177 GNDD Digital ground
TP175 CKEA0 Clock enable, SDRAM 0
TP176 CKEA1 Clock enable, SDRAM 1
Sheet 2 CPU/Demux
TP1155 5V M-PEG 5V MPEG supply voltage
TP1040 5V_OSC 5Vsupply voltage to 27MHz oscillator voltage
TP257 MCLK_SDC 27MHz oscillator feedback
TP243 27MHzCLK 27MHz clock
TP1034 27MHz OSC2 27MHz oscillator crystal
TP1032 27MHz OSC1 27MHz oscillator crystal
TP256 27MHzOUT 27MHz oscillator output collector
TP254 CLK_27_OSCOUT Biased 27MHz oscillator clock output to buffer IC
TP997 CLK_27_0 27MHz oscillator clock output 0
TP229 CLK_27_1 27MHz oscillator clock output 1
TP998 CLK_27_2 27MHz oscillator clock output 2
TP999 CLK_27_3 27MHz oscillator clock output 3
TP263 CLK_27_4 27MHz oscillator clock output 4
TP262 CLK_27_5 27MHz oscillator clock output 5
TP226 CLK_27_6 27MHz oscillator clock output 6
TP225 CLK_27_7 27MHz oscillator clock output 7
TP224 CLK_27_8 27MHz oscillator clock output 8
TP223 CLK_27_9 27MHz oscillator clock output to CPU PLL
TP1067 PDATA_DIR Control for parallel data bus
TP218 MCLK_54 54MHz clock output after resistor
TP1061 MCLK_54_CPU 54MHz clock output direct on IC
TP1137 TCK_CPU JTAG clock to CPU
TP1141 TCK_CPU JTAG clock to CPU
TP264 TDI_CI_DRAMC_LLC JTAG data input to DRAM
TP265 TMS_CI_DRAMC_LLC JTAG Test mode set for DRAM controller/IEEE 1394 LLC chip
TP266 TDO_CI_DRAMC_LLC JTAG data output
TP267 TCK_CI_DRAMC_LLC JTAG clock input
TP268 TRST_LLC JTAG reset input
TP215 TDI_CPU JTAG data input to CPU
TP214 TDO_CPU JTAG data output to CPU
TP213 TMS_CPU JTAG Test mode set for CPU
TP212 TCK_CPU JTAG clock to CPU
TP211 TRST_CPU JTAG reset to CPU
TP234 MPEG_TO_USER_IPL_B MPEG to user interprocessor link data
TP235 USER_TO_MPEG_IPL User to MPEG interprocessor link data
TP220 18M_CLOCK_RESET 18MHz clock reset
TP201 /CI_RESET /CI_RESET