Hitachi C28W40TN, Руководство по обслуживанию

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MICROCONTROLLER SECTION ON THE A8/D8 CHASSIS
INTRODUCTION:
The main microcontroller on the A8/D8 chassis is located at I001 (ST92R195B). This is an 80-pin QFP (quad-flat package) that is
surface mounted for compactness. This highly complex device controls many of the other integrated circuits via dedicated
input/output lines or the I2C bus. This device also generates the RGB signals for the on-screen display (OSD) menus and the
teletext. The device can acquire, decode and display the teletext without the need for a separate IC. This microcontroller is ROM-
less which results in the need of a separate memory device to store the program code necessary for operating the television. This
memory device is located at I002 and is multi-time programmable (MTP). This allows the device to be re-programmed and in the
future can even be re-programmed in the board without having to remove the back cabinet of the TV. The television stores all the
necessary customer preferences and operating settings in an on-board EEPROM (E2). This device can hold 2Kb of information for
storing the programme information (frequency, name, AV setting, etc.), factory alignment settings (geometry, white balance, tuner
AFC/AGC, etc.), service diagnostic errors and customer control settings (volume, brightness, contrast, etc.). This device
communicates with the main microcontroller via the I2C bus, even in the standby mode.
MAIN MICROCONTROLLER (I001)
INTRODUCTION
The ST92R195B is an enhanced microcontroller based on the ST9+ instruction set from STMicroelectronics. It is capable of
displaying menus and teletext for 50Hz and 100Hz televisions. This device can acquire/decode and display pages of teletext
information in FLOF (FastText) and TOP (only in Germany/Switzerland/Austria) modes. The device operates from a single 4MHz
crystal and a +5V supply. Dedicated address/data lines enable it to access 4Mbytes of address space, even though in this television
it is accessing 128Kbytes (1Mbit). These address/data lines are connected to the EPROM/MTP device which holds the instructions
necessary for controlling the television.
DESCRIPTION
EXTERNAL MEMORY INTERFACE MMU ADDRESS LINES
•
Pins 1 (MMU0), 15 (MMU1) and 16 (MMU2) are used to access addresses above 64Kbytes. Normally pins 15 and 16 are
not used when using a 128Kbyte EPROM/MTP device (MX26C1000APC) in position I002.
•
Pin 2 (MMU3) is used to select between either the EPROM/MTP in position I002, or a future device that can be fitted in
position I003. When this line is low, the MX26C1000APC device in position I002 is enabled (chip enable).
•
Pin 17 (MMU4) is used as an output port to derive a clock signal needed for shifting the data into the 74HC595 shift
register (I006).
•
Pin 18 (MMU5) is not used.
EXTERNAL MEMORY INTERFACE CONTROL LINES
•
Pin 4 is the Data strobe line which is connected to the output enable input of the EPROM/MTP (I002). When data is read
from the EPROM/MTP, this line is temporarily low.
•
Pin 8 is the Read/Write line for I003. Normally, this line is not used (HIGH) but if an SRAM were to be fitted into this
position, the line could be low when writing data to the SRAM.
EXTERNAL MEMORY INTERFACE ADDRESS LINES
•
Pins 3, 5, 6, 7, 13, 14 and 71 to 80 are the address lines needed to specify which location in a 64Kbyte page is needed to
be accessed from the EPROM/MTP (I002). These lines are also connected to I003 if an SRAM is to be fitted in future.
Normally these lines will be changing state (0V to approx. +5V). By placing an oscilloscope on pin 12 of the EPROM/MTP
(I002) it can be confirmed that the microcontroller is operating successfully. In this case, this line should be changing state
very frequently.
EXTERNAL MEMORY INTERFACE DATA LINES
•
Pins 63 to 70 are the 8 data lines needed for receiving data from the EPROM/MTP (I002). If an SRAM were to be fitted in
position I003, then these lines would be used to transfer data from the microcontroller to the SRAM. Under normal
circumstances these lines change from LOW (0V) to HIGH (approx. +5V).
GROUND CONNECTIONS
•
Pin 9 (GNDM) is the ground connection (0V) for the external memory interface. This should be free of noise to enable
successful communications between the microcontroller and the EPROM/MTP (or SRAM).
•
Pin 35 (GND) is the digital ground connection (0V) for normal operation of the device.
•
Pin 62 (GNDA) is the analogue ground connection for the DAC and phase lock loops (PLL’s).
SUPPLY CONNECTIONS
•
Pin 10 (VDDM) is the +5V supply for the external memory interface. Without this supply, the microcontroller cannot
communicate with the EPROM/MTP (or SRAM).
•
Pin 34 (VDD) is the main digital supply voltage to the IC (5V 10% tolerance).
•
Pin 52 (VDDA) is the analogue supply voltage for the DAC’s and PLL’s (+5V). These connections are all joined together
to the +5V standby rail of the television, ensuring that the microcontroller operates even in the standby state.