Hitachi C28W40TN, Руководство по обслуживанию

Страница: 32 / 394

31
FEC IC (IC802 / L64724)
The FEC IC is used in serial control mode with the communication through the I2C bus generated by the MPEG CPU. The data port
is used for both I2C clock and data lines, and to set the device address, which is set during initialisation, in this case the serial
control mode is selected by tying the ‘HOSTMODE’ pin low. R891, R892 are the serial I2C protection resistors and C777, C778 are
added to correct the timing of the I2C bus for this chip.
The master clock for the chip is the 54.864MHz generated by the COFDM IC.
The data input from the COFDM IC is in I/Q format through link resistors R848, R851, R852, R853, R854, R855.
The functions of the FEC (Forward Error Correction) IC are:
•
Quadrature decoding the data
•
Removing the inner and outer convolution coding
•
Viterbi decoding
•
Removing the descrambling (used to ensure an approximately balanced data signal)
•
Read-Solomon run-time coding (error protection) decoding.
•
Derivation of information about the error statistics of the signal
The information such as Bit Error Ratio (BER), used by the CPU internally and to generate the signal quality information for the user
is obtained from the FEC IC on the I2C bus.
The transport stream signal generated by the FEC IC contains the data to be processed, demultiplexed and decoded by the
Common Interface chips and the MPEG chipset on the MPEG PCB.
On PL807 this bus carries the following signals to the MPEG PCB:
•
8 bit wide parallel data
•
Data-valid
•
Packet start sync
•
Bit rate clock
Resistors are provided as an option for linking either packet start or error signals from the FEC but in this application the Common
Interface (to where the transport stream is linked) requires packet start. R878 should be fitted to allow this, and R877 omitted.
NVM
There are positions for two NVM chips, these can accommodate Atmel style 128kb and 256kb devices. Only one 256kb chip is
normally fitted at present (IC805) with it’s associated components C869, C893, R897 and R898. There is a ‘write-protect’ control line
provided from the CPU which disables any erroneous write operations.
RS232 SERIAL COMMUNICATIONS PORT
This chip performs the TTL to bipolar level conversion of the asynchronous serial communications link. It is made up of the AD202
IC (IC807) and it’s associated ladder/reservoir capacitors (C894, C895, C896, C897). The chip is powered from the 5V supply and
local decoupling is made up of C898, C899,
The link to the MPEG processor is TTL level with RX, TX, CTS, RTS signals. The connection to external devices is through a 9 pin
female D type socket at standard levels. Since the CPU UART peripheral is configured to use hardware flow control, the CTS is
pulled high at the output side by R792 in order to allow data to flow freely if no handshaking is provided.
V22 BIS MODEM SECTION
The Modem circuit consists of a Controller, Data Pump, and Data Access Arrangement (DAA)
The DAA provides a complete interface between data pump and a telephone line. All functions are integrated into a single hybrid
module which provides high voltage isolation.
When Loop Control is at logic 0, an active line termination is applied across Tip and Ring, at which time the device can be
considered off-hook and DC loop current will low. This is used to seize the line for an outgoing call, or if it is applied and
disconnected at the required rate, can be used to generate dial pulses. The receiver is not designed to respond to any incoming
calls.
When Off-hook, the DAA converts the balanced 2-wire input presented by the line at Tip and Ring, to a ground referenced signal at
VX. Conversely the device converts the ground referenced signal input at VR to a balanced 2-wire signal across Tip and Ring.
The Loop pin provides a voltage that is proportional to the voltage across Tip and Ring. This can be used with external circuitry to
detect a parallel phone going off-hook, and the presence of a ringing voltage.
The parallel phone detect circuit uses the loop voltage to detect a short small scale pulse. Two R-C time constants are used to
remove noise spikes, and DC information. A parallel phone going off-hook will result in a ~1s pulse going to the MPEG processor.
The ring detect circuit is a comparator that converts the loop voltage into a series of logic pulses which is passed to the controller.
The Data Pump is a synchronous single-chip modem which provides a means to construct a V.22bis modem capable of 2400 bps
full duplex over dial-up lines.
Operating over the Public Switched Telephone Network (PTSN), the Z02201 meets the modem standards for V.22bis, V.22, V.23,
V.21, Bell212A, and Bell 103.
The Z02201 performs HDLC framing at all speeds. All modulation, demodulation, filtering, A/D and D/A conversion functions for
transmit and receive are provided on-chip.