42
•
Smartcard port - the main smartcard driver port (SC0x) is used to carry all the low level controls for the CA (Conditional
Access) smartcard – reset, clock, data I/O, etc. These lines are protected by resistor / diode networks (R257 - R262,
R266, D201- D206, D209) and linked to the smartcard PCB which is mounted in the analogue section through PL204.
The CPU has a number of parallel port pins which are used to control various functions on the COFDM and MPEG PCBs,
these are:
Port Identification
Input / Output
Function
GP1040
O
22kHz enable for QPSK use
GP1041
O
TS/NPES
GP1042
O
NVM write-protest
GP1043
O
Reset for PAL encoder and AV decoder ICs
GP1044
I
ROM_SIZE, input sense pin
GP1045
O
Reset for front_end PCB
GP1046
O
Reset pulse for 18MHz clock gate on front-end PCB
GP1047
O
Reset for Common Interface ICs
GP1048
O
Reset for IEEE1394 chip
GP1049
I
Modem off-hook input
•
Local CPU memory control
•
Internal cache – this is internal to the CPU
•
DRAM control – the CPU has a dedicated control interface for the main DRAM. Addressing for 16Mbit (IC201) is provided
and EDO type DRAM is used.
Address decoding within CI A (based on CS2) allows access to the ‘CS miss’ devices for which the chip selects are generated in the
CI A device, the timing for these data communications is then provided using the DSACK controls.
For functional reasons each interrupt group is made up of a pair, each representing an internal and an external input (12 into 6
levels), each interrupt pair is assigned a group, and the groups are prioritised. The system interrupts are allocated as follows:
Group
Function
Triggering
Level / edge
Priority
External INT 4 / Internal NMI
Level
Highest
4
Timer (0-2) / RES
Selectable
/\
3
External INT 3 / PID processor
Selectable
l
2
External INT 2 / Teletext / I2C / UARTS
Selectable
l
1
External INT 1/ Smartcard
Selectable
\/
0
External INT 0 / 1284
Selectable
Lowest
External Interrupts are mapped as follows
•
EXTERNAL INT 4:External DRAM controller
•
EXTERNAL INT 3:Common Interface B
•
EXTERNAL INT 2:1394
•
EXTERNAL INT 1:Common Interface A
•
EXTERNAL INT 0:A/V Decoder
Note: The external interrupts have been re-arranged to enable debug on IRQ 4 while the DRAM controller is not being fitted.
The internal memory map is as below.
Содержание C28W40TN
Страница 29: ...28 GENERAL BLOCK DIAGRAM ...
Страница 91: ...90 CASE DE FONCTIONS EXTRÉMITÉ HAUTE CASE FONCTIONS EXTRÉMITÉ BASSE ...
Страница 102: ...101 SCHÉMA SYNOPTIQUE ...
Страница 165: ...164 HÖHERE FEATURE BOX NIEDRIGE FEATURE BOX ...
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Страница 299: ...Users Guide C28W40TN C32W40TN ...
Страница 351: ...notes ...
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Страница 355: ...Users Guide C28W35TN C32W35TN S C R E E N S C R E E N ...