Hitachi C28W40TN, Руководство по обслуживанию

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MPEG DECODER AND AV/GRAPHICS PCB
RESET CIRCUIT
The initial power-on-reset (active low) for the CPU is generated by IC202 by monitoring the incoming 3V3 power line, with a ‘reset’
threshold at 2.9V, this signal is an active low. The output of the generator is functionally ‘OR’d with an input (active high) through
PL203 into Q200, R207, R208 from the mother board (STB or IDTV) processor which is able to force a reset of the CPU if
necessary. An inverter is provided (IC210) but not used at present.
Reset Circuit Arrangement
After the CPU is reset it generates resets through output ports for the other devices on the COFDM and MPEG PCBs timed to
guarantee the correct start-up of the circuitry on both PCBs (see CPU section). These are used for:
•
COFDM/FEC
•
PAL video encoder
•
AV chip
•
Common Interface chips A and B
MASTER CLOCK OSCILLATOR
On the MPEG PCB the system uses a single master clock VCXO centred at 27.000MHz. This is generated using a Colpitts crystal
oscillator (R248, R242, R243, R244, R212, R213, R218, R214, R217, R215, R216, L202, C237, C220, C231, C215, C206, C207,
C232, C233, C234, X200, D200, Q201). The frequency is controlled by the varicap diode (D200) with it’s DC feed from the output of
the filter section (R248, R244, R243, R242, C231, C215). The oscillator is locked to the incoming data by the PLL in the demux IC
(see below). The supply for the oscillator is decoupled through L202. The oscillator output from the emitter of Q201 is AC coupled
and biased for the clock buffer following through C234, R215, R216.
The output of the oscillator is buffered and distributed through the clock IC (IC207) which uses separate outputs for each load
device. The outputs are used for: CPU/demux IC Common Interface A and B AV decoder Video encoder Audio PLL IEEE1394 – this
is currently not supported External DRAM controller – this is currently not supported There are currently 3 unused outputs from the
clock buffer IC
Local decoupling is used (C271 - C274). Provision has been made for clock termination resistors on each chip.
AUDIO CLOCK PLL
The PLL function for the audio decoder clock is carried out by IC220. This uses the 27MHz oscillator as it’s input from the clock
buffer and produces an output at the correct frequency for the audio oversampling clock to the AV chip (256 times the audio sample
rate) as signalled in the transmission. The frequency is controlled by 3 static lines from the CI A IC (IC400), see table following. A
second output is available at 1.862MHz for a UART, this is not used. The chip is decoupled by C276.
Signal Path Diagram for Audio PLL IC