3 Development Board Circuit
3.9 MIPI/LVDS
DBUG388-1.0E
18(22)
3.9.3
Pins Distribution
Table 3-7 J15 FPGA Pin Distribution
Signal Name
Pin No.
Socket Pin No.
BANK
Description
I/O Level
F_LVDS_A1_P
28
1
2
Differential output
channel 1+
2.5V(LVDS)/
1.2V(MIPI)
F_LVDS_A1_N
27
2
2
Differential output
channel 1-
2.5V(LVDS)/
1.2V(MIPI)
GND
-
3
-
-
-
GND
-
4
-
-
-
F_LVDS_A2_P
30
5
2
Differential output
channel 2+
2.5V(LVDS)/
1.2V(MIPI)
F_LVDS_A2_N
29
6
2
Differential output
channel 2-
2.5V(LVDS)/
1.2V(MIPI)
GND
-
7
-
-
GND
-
8
-
-
F_LVDS_A3_P
32
9
2
Differential output
channel 3+
2.5V(LVDS)/
1.2V(MIPI)
F_LVDS_A3_N
31
10
2
Differential output
channel 3-
2.5V(LVDS)/
1.2V(MIPI)
GND
-
11
-
-
GND
-
12
-
-
F_LVDS_A4_P
35
13
2
Differential output
channel 4+
2.5V(LVDS)/
1.2V(MIPI)
F_LVDS_A4_N
34
14
2
Differential output
channel 4-
2.5V(LVDS)/
1.2V(MIPI)
GND
-
15
-
-
GND
-
16
-
-
GND
-
17
-
-
GND
-
18
-
-
GND
-
19
-
-
GND
-
20
-
-