3 Development Board Circuit
3.10 RS232
DBUG388-1.0E
20(22)
3.10
RS232
3.10.1
Overview
One RS232 interface is reserved on the development board for the
FPGA to communicate with PC or the other devices.
3.10.2
RS232 Circuit
Figure 3-9 RS232 Download Connection
UART_TXD
UART_RXD
DB9
UART_TX
UART_RX
19
20
J2
U1
GW1NS4/GW1NSR4/GW1NSER4
MAX3232
U4
3.10.3
Pins Distribution
Table 3-9 RS232 Pins Distribution
Signal Name
Pin No.
BANK
Description
I/O Level
UART_TXD
19
3
Serial data
Sends from FPGA
1.8V
UART_RXD
20
3
Serial data
Sends to FPGA
1.8V