2 Development Board Introduction
2.4 System Block Diagram
DBUG388-1.0E
6(22)
2.4
System Block Diagram
Figure 2-4 System Block Diagram
J-Link
LDO
1.2V/1.8V/2.5V/
3.3V
1*BUTTON
OSC
50MHz
FT232HL
GPIO
1*LED
MINI USB
4*SWITCH
5V
5 Pairs LVDS/MIPI INPUT
4Pairs
LVDS/MIPI
OUTPUT
1*UART
1*SPI Flash
FPGA
2.5
Features
The structure and feature of the development board are as follows:
5.
FPGA
Adopts QN48 package
Up to 38 user I/O
Embedded flash, data not easily lost if power down
Abundant LUT4 resources
Multiple modes and capacities of B-SRAM
6.
FPGA Configuration Modes
JTAG
AUTO BOOT
7.
Clock resource
50MHz Clock Crystal Oscillator