Giga-tronics GT 9000, Руководство по эксплуатации и техническому обслуживанию

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3.3.16 Divide-By-N — PC Assembly A17
This circuit is a programmable frequency divider. It is set by the computer with a divisor
between 95 and 395. Its frequency input is the 95 to 395 MHz IF from the reference mixer. The
divided IF is supplied to the output phase lock loop and should be exactly 1 MHz when the
output loop is locked. A two-stage amplifier provides enough gain throughout the operating
frequency range to drive the Mod-8/9 counter (U11). AR1 and AR2 are amplifiers. CR1,2 and
C23 detect the level of the signal at the output of AR1, and U12A and Q1 provide bias to CR3,
CR4, CR7 and CR8 to attenuate the signal as required, thereby providing a form of automatic
level control. L2, C24 and C27 are required for power supply filtering. L3, C54, C55, and L1,
C25, C22 are low pass filters for the IF signal.
In the discussion of the divider circuit, terms are defined as follows:
•
IF cycles refers to the amplified IF from the reference mixer, which is used as a timing clock
by the Mod 8/9 counter.
•
Clock cycles refers to the output of the Mod 8/9 counter, U11-2, which is used as a timing
clock by the 3-bit and 6-bit counters.
•
Division cycles refers to the output signal, U9-14, which should have a rate of 1 MHz when
the loop is locked.
IF cycles are the fastest of the three; division cycles are the slowest.
The divisor, selected by the computer, is supplied as a 9-bit binary number at TTL level to the
10124 translators (U1, 2 and 3), which convert the bits to ECL levels. Bits 0, 1 and 2 control
the 3-bit counter (U5) and bits 3 through 8 control the 6-bit counter consisting of U4, 6 and 7.
These two counters operate independently, but they use the same timing clock and they count
down simultaneously.
The outputs of the 3-bit counter U5, by way of gate U8, program the Mod-8/9 counter U11.
While U5 is counting down, U11 divides the IF by 8. In the case of most divisors, it is
necessary for the IF to be divided by 9 for some portion of the division cycle; only when the
three lowest bits are all zero is U11 programmed as a Mod-8 counter throughout the division
cycle (a situation which can only occur if the divisor itself happens to be an even multiple of 8).
Whenever it reaches zero, U5 stops counting until it is preset at the next division cycle.
The 6-bit counter (U6 and U7) continues counting down after U5 has reached zero and U11 has
entered the Mod-8 phase of the division cycle. The lowest number it ever counts down from is
11, (binary 001011) whereas the highest number the 3-bit counter ever counts down from is 7
(binary 111); therefore the 3-bit counter always finishes first. When the 6-bit counter has
completed its count, gate U8-14 goes high; this line, applied to U9D, allows U9-14 to go low
(this represents the falling edge of the output waveform) on the next clock transition. The output
is also used to pre-set the 6-bit counter. The 3-bit counter is pre-set by U9-2; this transition
occurs a half-cycle later than for the other counter because U9-2, unlike U9-15, is triggered by
the complement of the divider circuit clock (U11-3). The delays involved in driving the output
low, presetting the counters, and triggering them to count down again result in the addition of
two clock cycles to the division cycle (i.e., U11 will perform two extra divisions by 8 before the
next division cycle can begin). To compensate for this, the U6 Q1 output is not connected to the
U8-14 OR gate; the 6-bit counter counts down only to 2, not to zero, before sending the high
level to U9 that initiates the output transition and presets the counters. The duration of the
output low pulse is one clock cycle, which is equal to eight IF cycles. Because the IF is
variable, the width of the low pulse varies (between about .02 and .08 microseconds).
Model GT 9000 Microwave Synthesizer
3-30
Manual No. 120AM00250, Rev C, September 1998