Giga-tronics GT 9000, Руководство по эксплуатации и техническому обслуживанию

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3.2.5 The Output Loop
Up to three fundamental YIG oscillators are needed to generate the RF output. The ranges of the
individual YIGs are 2 to 8 GHz, 8 to 20 GHz, and 20 to 26.5 GHz. Frequencies up to 2 GHz are
produced by downconversion (mixing and/or dividing the outputs of two oscillators to obtain an
intermediate frequency). The frequency of a YIG oscillator is controlled by means of (1) its
tuning coil and (2) its FM coil.
The tuning coil is used for coarse tuning under the direct control of the computer. The computer
sends digital data to the YIG driver circuit, where a digital-to-analog converter and an amplifier
turn this data into a controlled current supply to the YIG tuning coil. In this way the oscillator
can be tuned to within about 10 MHz of the desired output frequency.
The FM coil is used for fine tuning of the oscillator under the control of the output phase lock
loop circuit. The output PLL controls the current through the FM coil in order to phase-lock the
YIG to the PLL reference frequency.
When the operator selects an output frequency, the computer selects the appropriate YIG
oscillator and (using the tuning coil) coarse-tunes it to within about 10 MHz of the desired
output. The signal produced by this YIG will, at some point in the RF path, pass through a
coupler which will return a sample of it to the reference mixer.
The other input to the reference mixer is not generated within the output loop; it comes from
the reference loop, and is generated by the 1.9 to 8.7 GHz YIG (the reference YIG). This
reference frequency is selected by the computer and is 95 to 395 MHz lower than the frequency
of the output YIG. The IF output of the reference mixer is equal to this difference between
reference and output frequencies (in other words, the IF output has a range of 95 to 395 MHz).
The output loop requires a 1 MHz signal from the divide-by-N circuit regardless of the output
frequency, because the output loop phase detector compares the output of the divide-by-N with
a timebase-derived 1 MHz reference. Therefore, the divide-by-N must be programmed so as to
divide the mixer IF down to 1 MHz (the range of divisors for this circuit is 95 to 395). The
divisor (N) selected by the computer is equal to the mixer IF, in MHz. If the mixer IF is
195 MHz, N is set to 195. The 195 MHz IF is divided by 195 and a 1 MHz quotient results. The
output PLL then compares its two 1 MHz inputs, and adjusts the current in the FM coil of the
output YIG oscillator in order to achieve and maintain phase lock.
For example, if the user requests a 3000 MHz RF output, the computer selects the 2 to 8 GHz
YIG and tunes it to 3000 MHz, but only roughly (the YIG could, at this point, be generating
2994 or 3003 MHz, for example). At the same time, the computer selects the appropriate
reference frequency (in this case 2905 MHz) and the appropriate divisor for the divide-by-N
circuit (in this case 95, since there is a 95 MHz difference between the two loops).
A sample of the output frequency is furnished to the reference mixer by means of a coupler in
the RF path. The other input to the mixer is the 2905 MHz reference frequency. The mixer
produces an IF equal to the difference between the reference and output frequencies. The
divide-by-N circuit, as programmed by the computer, divides this IF by 95 and supplies the
result to the output phase lock loop.
However, since the output oscillator is not precisely tuned to 3000 MHz, the two loops will not
be precisely 95 MHz apart, the mixer IF will not be precisely 95 MHz, and the result of
dividing the IF by 95 will not be precisely 1 MHz. The output phase lock loop must correct the
error.
Model GT 9000 Microwave Synthesizer
3-6
Manual No. 120AM00250, Rev C, September 1998