GEViCAM GP-151400, Руководство по эксплуатации

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GEViCAM Inc
3. Operations
3.1 GigE Camera Function Blocks
•
Imager Block
The Imager block is specific to imager type and it contains the imager driver circuit. By simply
changing this block (single PC board), many types of resolution, size, characteristics of CCD and
CMOS sensors are adapted to the same platform while other blocks remain in the same hardware.
•
Signal Process Block
The signal process section is critical to the high performance and the image quality. The 12-bit
high speed A/D conversion is standard for all models. On this board, a RJ-45 connector is
mounted with the shortest traces from the PHY chip.
•
GigE Block
The GigE Block consists of a FPGA, PHY and memory ICs.
•
FPGA
♦
Timing Gen Block
This is a control logic and timing generator block for the camera. The design prince
ple is register base and easy to reprogram various imager types without effecting
other functions.
♦
iPort (Pleora core) Block
The heart of GigE interface and frame grabber function control is in this block.
♦
PLC (Programmable Logic Controller)
The GPIO function interface is called PLC as it generates necessary functions for
PLC interface.
•
PHY
A low power, small package PHY chip is used in a very dense layout. The heat dissipation I
s carefully removed to outside with the heat-pipe architecture for the high reliability opera
tion.
•
Memory
A fame grabber function requires large memory space. The standard size is 16 MB but can
be extended to 64 MB as the custom option.
•
Power and GPIO
This block seems simple but creates the
major differences from other cameras.
Low power consumption, extremely low
noise characteristics and unique GPIO
functions are the result of our expertise
based on many years of design experience.
•
Easy Customization
This is the very refined platform design and easy to build
custom-design products out of these blocks. The blocks
of Imager, Signal and GPIO boards are easily customized.
Please contact GEViCAM for the specific requirement.
Imager
Block
Signal Block
Power and GPIO
Timing
Gen
i-Port
PHY
Memory Block
Fig. 12