General Standards Corporation PCI-DIO24PMC-DIO24PCI-DIO24-GD1 Скачать руководство пользователя страница 23

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DIO24, User Manual

5.1.10. PCI Base Address Register for I/O Access to Local/Runtime/DMA Registers

(Offset 0x14, Reset 0x00000001)

Memory Space Indicator
A ‘1’ indicates the register maps into I/O space.
Note: Hardcoded to 1.

D1 Reserved
D7:2

I/O Base Address.
Default Size = 256 bytes.
Note: Hardcoded to 0.

D31:8 I/O Base Address.

Base Address for I/O access to Local, Runtime, and DMA Registers.

Note: PCIBAR1 is I/O Mapped Base Address of PCI9080 Registers

5.1.11. PCI Base Address Register for Memory Access to Local Address Space 0

(Offset 0x18, Reset 0x00000000)

Memory Space Indicator
A ‘0’ indicates register maps into Memory space.
(Specified in Local Address Space 0 Range Register - LAS0RR.)

D2:1

Location of register (if memory space). Location values:
00 - Locate anywhere in 32-bit memory address space
(Specified in Local Address Space 0 Range Register - LAS0RR.)

D3 Prefetchable

A ‘0’ indicates reads are not prefetchable.
(Specified in Local Address Space 0 Range Register - LAS0RR

D31:4 Memory

Base

Address

Memory base address for access to Local Address Space 0.

5.1.12. PCI Subsystem Device/Vendor ID Register

(Offset 0x2C, Reset 0x908010B5)

D15:0 Subsystem Vendor ID – 0x10B5 = PLX Technology
D31:16 Subsystem Device ID – 0x2606 = General Standards Corporation DIO24, 0x2400 = General

Standards HPDI32 (used by PCI-DIO24-GD1).

5.1.13. PCI Interrupt Line Register

(Offset 0x3C, Reset 0x00)

D7:0

Interrupt Line Routing Value. Indicates which input of the system interrupt controller(s) to which
the interrupt line of the device is connected.

5.1.14. PCI Interrupt Pin Register

(Offset 0x3D, Reset 0x01)

D7:0

Interrupt Pin register. Indicates which interrupt pin the device uses.
01=INTA#

Note:

PCI 9080 supports only one PCI interrupt pin (INTA#).

General Standards Corporation, Phone: (256) 880-8787

Содержание PCI-DIO24PMC-DIO24PCI-DIO24-GD1

Страница 1: ...Manual Manual Revision June 12 2002 General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 Fax 256 880 8788 URL www generalstandards com E mail sales generalstand...

Страница 2: ...DIO24 User Manual 2 General Standards Corporation Phone 256 880 8787...

Страница 3: ...sume any liability arising out of the application or use of any product or circuit described herein nor is any license conveyed under any patent rights or any rights of others General Standards Corpor...

Страница 4: ...1 FPGA EPROM U42 13 2 4 2 Termination Resistors RP1 RP7 13 2 5 Cables 14 2 5 1 Loop Back Test Cable 14 3 Operation 15 3 1 Identification 15 3 2 Reset 15 3 3 I O Programming 15 3 4 I O Reads and Writes...

Страница 5: ...CI Subsystem Device Vendor ID Register 23 5 1 13 PCI Interrupt Line Register 23 5 1 14 PCI Interrupt Pin Register 23 5 1 15 PCI Min_Gnt Register 24 5 1 16 PCI Max_Lat Register 24 5 2 Local Configurati...

Страница 6: ...0 Table 2 Register level identification of the PCI DIO24 GD1 11 Table 3 External I O connector P1 pins and descriptions 11 Table 4 Register level identification of the DIO24 15 Table 5 Register map of...

Страница 7: ...e external I O interface is variable see below The external interface includes 24 pins that can be arbitrarily programmed as either input or output and one pin that is input only The 24 programmable p...

Страница 8: ...with your specifications to inquire about a custom application 1 7 Reference Material The following reference material may be of particular benefit in using the DIO24 The specifications provide the i...

Страница 9: ...DIO24 User Manual GLOBAL ENGINEERING DOCUMENTS 15 Inverness Way East Englewood CO 80112 Phone 800 854 7179 http global ihs com 9 General Standards Corporation Phone 256 880 8787...

Страница 10: ...odel number includes RS485 transceivers The transceivers are the 25 small gray outlined squares in Figure 2 running down the center of the board If the transceivers have four unpopulated solder pads t...

Страница 11: ...ologies PCISID 0x2400 This identifies the board as a member of the HPDI32 product series FRR 0xXX0BXXXX The value in the third byte identifies this as a DIO24 2 2 Connectors 2 2 1 External I O Connect...

Страница 12: ...D1 45 PORT C D6 21 PORT B D2 46 PORT C D6 22 PORT B D2 47 PORT C D7 23 PORT B D3 48 PORT C D7 24 PORT B D3 49 Dedicated INPUT Clk Out 25 PORT B D4 50 Dedicated INPUT Clk Out 2 3 Jumpers 2 3 1 Jumper B...

Страница 13: ...the jumper is removed the bit returns a zero 0 In the default factory configuration this jumper is installed One potential use of the jumper is to aid in distinguishing individual boards when multipl...

Страница 14: ...unctionality of both the DIO24 and the corresponding device driver On this cable all three ports are wired in parallel such that all Port A pins are wired directly to the same identical pins for both...

Страница 15: ...the given register write cycle A reset programs all I O pins as inputs and programs the data output latches to zero 3 3 I O Programming The I O pins are programmed via the I O Control Register One bit...

Страница 16: ...tion process The registers occupy a block of 256 contiguous bytes accessible as bytes words or long words PCIBAR0 gives the block s base address in memory space PCIBAR1 gives the block s base address...

Страница 17: ...set Writing a one here resets the board The IOCR and DDOR are programmed to zero The bit clears itself The operation is completed within a single PCI bus access cycle Writing a zero has no affect 4 3...

Страница 18: ...PC0 Port C Pin 0 This controls the direction of Port C bit 0 1 PB Port B This controls the direction of all eight Port B bits 0 PA Port A This controls the direction of all eight Port A bits 4 3 5 Di...

Страница 19: ...Field Description 31 24 Reserved 24 DI Dedicated Input This is the input value for the state of the Dedicated Input pin 23 16 PORTC Port C This is the input value for the state of the Port C pins 15 8...

Страница 20: ...ST Unused Header Type Latency Timer Cache Line Size 0x00002008 0x10 0x10 Y PCI Base Addr 0 for Memory Mapped Local Runtime DMA Registers PCIBAR0 0x00000000 0x14 0x14 Y PCI Base Addr 1 for I O Mapped L...

Страница 21: ...elf or observed PERR asserted 2 PCI9080 was bus master for the operation in which the error occurred 3 Parity Error Response bit in the Command Register is set Writing a 1 to this bit clears the bit D...

Страница 22: ...of PCI bus clocks the amount of time the PCI9080 as a bus master can burst data on the PCI bus 5 1 8 PCI Header Type Register Offset 0x0E Reset 0x00 D6 0 Configuration Layout Type 0 D7 Header Type 0 5...

Страница 23: ...y address space Specified in Local Address Space 0 Range Register LAS0RR D3 Prefetchable A 0 indicates reads are not prefetchable Specified in Local Address Space 0 Range Register LAS0RR D31 4 Memory...

Страница 24: ...F000 0x04 0x84 Y Local Base Address Remap for PCI to Local Address Space 0 Unused 0x00000000 0x08 0x88 Y Mode Arbitration Register 0x00000000 0x0C 0x8C Y Big Little Endian Descriptor 0x00000000 0x10 0...

Страница 25: ...ority 01 Channel 2 priority 10 Channel 1 priority 11 Reserved D21 Local bus direct slave give up bus mode A value of 1 indicates local bus will be released when PCI9080 write FIFO empty or read FIFO f...

Страница 26: ...4 Y Mailbox Register 1 Unused 0x00000000 0x48 0xC8 Y Mailbox Register 2 Unused 0x00000000 0x4C 0xCC Y Mailbox Register 3 Unused 0x00000000 0x50 0xD0 Y Mailbox Register 4 Unused 0x00000000 0x54 0xD4 Y...

Страница 27: ...s to a Target D31 28 PCI Mailbox 3 0 Write Status 5 3 2 Serial EEPROM Control PCI Command Codes User I O Control Init Control Register PCI 0x6C Reset 0x0x001767E D3 0 PCI Read Command Code for DMA D7...

Страница 28: ...r Manual 5 4 DMA Registers The DMA Registers are not used on the DIO24 5 5 Messaging Queue Registers The Messaging Queue Registers are not used on the DIO24 28 General Standards Corporation Phone 256...

Страница 29: ...3 2001 Initial Release December 11 2001 Added Plug and Play information February 13 2002 Added system resource and loop back cable information October 23 2002 Added information about the new subsystem...

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