DIO24, User Manual
5.1.4. PCI Revision ID Register
(Offset 0x08)
D7:0
Revision ID - The silicon revision of the PCI9080.
5.1.5. PCI Class Code Register
(Offset 0x09-0B, Reset=0x068000)
D7:0
Register level programming interface
0x00 = Queue Ports at 0x40 and 0x44.
0x01 = Queue Ports at 0x40 and 0x44, Int Status and Int Mask at 0x30 and 0x34
D15:8 Sub-class Code - 0x80 = Other bridge device.
D23:16 Base Class Code. - 0x06 = Bridge Device
5.1.6. PCI Cache Line Size Register
(Offset 0x0C, Reset 0x00)
D7:0
System cache line size in units of 32-bit words.
5.1.7. PCI Latency Timer Register
(Offset 0x0D, Reset 0x00)
D7:0
PCI Latency Timer. Units of PCI bus clocks, the amount of time the PCI9080, as a bus master, can
burst data on the PCI bus.
5.1.8. PCI Header Type Register
(Offset 0x0E, Reset 0x00)
D6:0
Configuration Layout Type = 0
D7
Header Type = 0.
5.1.9. PCI Base Address Register for Memory Access to Local/Runtime/DMA Registers
(Offset 0x010, Reset 0x00000000)
D0
Memory Space Indicator
A ‘0’ indicates register maps into Memory space.
Note: Hardcoded to 0.
D2:1
Location of Register:
00 - Locate anywhere in 32-bit memory address space
Note: Hardcoded to 0.
D3 Prefetchable.
Note: Hardcoded to 0.
D7:4
Memory Base Address.
Default Size = 256 bytes.
Note: Hardcoded to 0.
D31:8 Memory Base Address.
Memory base address for access to Local, Runtime, and DMA registers.
Note: PCIBAR0 is Memory Mapped Base Address of PCI9080 Registers
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