DIO24, User Manual
4. Registers
This section gives a description of the DIO24 register map and all DIO24 registers. The GSC specific registers are
covered in detail. The PLX PCI9080 registers are covered is less detail. The full DIO24 register map consists of PCI
specific registers, internal PLX PCI9080 registers and GSC specific registers. In the paragraphs that follow offsets
are given in bytes and register sizes are given in bits. Register access types are “RO” for read-only, “RW” for
read/write, “WO” for write-only, and “W1” for write-once. If the access is given as “*” it means that the access
details are given with the register’s description.
4.1. PCI Configuration Registers
The PCI Configuration Registers are built into the DIO24’s PCI interface chip, which is the PLX PCI9080. This set
of registers is governed by the PCI bus specification. Access to these registers is via PCI bus cycles and is beyond
the scope of document. Read the details of these registers before using them. The PCI registers are described in
section 5.1.
4.2. PLX PCI9080 Internal Registers
These registers are provided as a part of the feature set for this PCI interface chip. The chip is hardwired so that PCI
registers PCIBAR0 and PCIBAR1 identify where these internal registers are located. These registers are set during
the system’s PCI enumeration and initialization process. The registers occupy a block of 256 contiguous bytes,
accessible as bytes, words or long words. PCIBAR0 gives the block’s base address in memory space. PCIBAR1
gives the block’s base address in I/O space. Read the details of these registers before using them. The PCI9080
internal registers are described beginning in section 5.2.
4.3. GSC Specific Registers
These registers are provided as a part of the feature set for the DIO24. The location and size of the GSC specific
register block is determined by accessing PCI registers PCIBAR2. The address is generally determined by the BIOS
during the boot up process. The size of the block is specified by the DIO24 as 5
1
2 bytes. PCIBAR2 is configured to
give the base address in memory space. The following gives details of the GSC specific registers. All offsets are
given relative to the register block’s base address.
Table 5
Register map of the GSC specific registers.
Offset Size Access Register
Name
0x00
32
RO
Firmware Revision Register (FRR)
0x04
32
RW
Board Control Register (BCR)
0x08
32
RO
Board Status Register (BSR)
0x60
32
RW
I/O Control Register (IOCR)
0x64
32
RW
Discrete Data Output Register (DDOR)
0x68 32 RO Discrete
Data Input Register (DDIR)
* All other locations within the register block are reserved.
4.3.1. Firmware Revision Register (FRR, 0x00, 32, RO)
This register gives revision and type information for the board and the firmware.
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Field
SID
Default
1 0 0 0 0 0 0 0
0x0B
16
General Standards Corporation, Phone: (256) 880-8787
