General Standards Corporation PCI-DIO24PMC-DIO24PCI-DIO24-GD1, Руководство пользователя

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DIO24, User Manual
5. PLX PCI9080 Registers
These registers are provided by the PCI interface chip, which is the PLX PCI9080. Since many of the PCI9080
features are not utilized in on the DIO24, it is beyond the scope of this document to duplicate the
PCI9080 User’s
Manual
. Only those registers that clarify DIO24 details are given here. Please refer to the
PCI9080 User’s Manual
(see Related Publications) for more detailed information.
5.1. PCI Configuration Registers
NOTE: Most PCI configuration registers are initialized by a system’s BIOS or firmware at boot
time. Additionally, information on PCI configuration registers is normally of more use to device
driver writers then to application writers.
Table 6
Register map of the PCI Configuration Registers.
PCI
CFG
Addr Local
Offset
Addr
PCI/Local
Writable
Register Name
Value after
Reset
0x00 0x00 Local Device ID/Vendor ID 0x908010B5
0x04 0x04 Y Status/Command 0x02800017
0x08 0x08 Local Class Code/Revision ID 0x0680003
0x0C 0x0C Y[15:0], Local BIST (Unused)/Header Type/Latency Timer/Cache Line Size 0x00002008
0x10 0x10 Y PCI Base Addr 0 for Memory Mapped Local/Runtime/DMA
Registers (PCIBAR0) 0x00000000
0x14 0x14 Y PCI Base Addr 1 for I/O Mapped Local/Runtime/DMA
Registers (PCIBAR1) 0x00000001
0x18 0x18 Y PCI Base Addr 2 for Local Addr Space 0 (PCIBAR2) 0x00000000
0x1C 0x1C Y PCI Base Addr 3 for Local Addr Space 1 (PCIBAR3)
(Unused) 0x00000000
0x2C 0x2C Local Subsystem ID/Subsystem Vendor ID 0x10B52606/
0x10B52400
0x30 0x30 Y PCI Base Address to Local Expansion ROM (Unused) 0x00000000
0x3C 0x3C Y[7:0], Local Max_Lat/Min_Gnt/Interrupt Pin/Interrupt Line 0x00000100
5.1.1. PCI Configuration ID Register
(Offset 0x00, Reset 0x908010B5)
D15:0 Vendor ID –– 0x10B5 = PLX Technology
D31:16 Device ID –– 0x9080 = PCI9080
5.1.2. PCI Command Register
(Offset 0x04, Reset 0x0017)
D0 I/O Space
A ‘1’ allows the device to respond to I/O space accesses.
D1 Memory Space
A ‘1’ allows the device to respond to memory space accesses.
D2 PCI Master Enable.
A ‘1’ allows the device to behave as a PCI bus master.
Note:
This bit must be set for the PCI 9080 to perform DMA cycles
.
D3 Special Cycle. (
Not Supported
.)
D4 Memory Write/Invalidate.
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