DIO24, User Manual
A ‘1’ enables memory write/invalidate.
D5
VGA Palette Snoop. (
Not Supported
.)
D6
Parity Error Response
‘0’ indicates that a parity error is ignored and operation continues.
A ‘1’ indicates that parity checking is enabled.
D7
Wait Cycle Control. Controls whether the device does address/data stepping.
A ‘0’ indicates the device never does address/data stepping.
Note:
Hardcoded to 0.
D8 SERR#
Enable
A ‘1’ allows the device to drive the SERR# line.
D9
Fast Back-to-Back Enable. Indicates what type of fast back-to-back transfers a Master can perform
on the bus.
A ‘1’ indicates fast back-to-back transfers can occur to any agent on the bus.
A ‘0’ indicates fast back-to-back transfers can only occur to the same agent as the previous cycle.
D15:10 Reserved
5.1.3. PCI Status Register
(Offset 0x06, Reset 0x0280)
D5:0 Reserved
D6
User Definable Features Supported
A ‘1’ indicates UDF are supported.
Note:
User Definable Features are Not Implemented
D7
Fast Back-to-Back Capable.
A ‘1’ indicates the adapter can accept fast back-to-back transactions.
D8
Master Data Parity Error Detected
A ‘1 indicates the following three conditions are met:
1. PCI9080 asserted PERR# itself or observed PERR# asserted.
2. PCI9080 was bus master for the operation in which the error occurred.
3. Parity Error Response bit in the Command Register is set.
Writing a ‘1’ to this bit clears the bit.
D10:9 DEVSEL Timing. Indicates timing for DEVSEL# assertion.
A value of ‘01’ indicates a medium decode.
Note: Hardcode to 01.
D11 Target
Abort
A ‘1’ indicates the PCI9080 has signaled a target abort. Writing a ‘1’ to this bit clears the bit.
D12 Received
Target
Abort
A ‘1’ indicates the PCI9080 has received a target abort. Writing a ‘1’ to this bit clears the bit.
D13
Master
Abort
A ‘1’ indicates the PCI9080 has generated a master abort signal. Writing a ‘1’ to this bit clears the
bit.
D14 Signal
System
Error
A ‘1’ indicates the PCI9080 has reported a system error on the SERR# signal. Writing a ‘1’ to this
bit clears the bit.
D15
Detected Parity Error
A ‘1’ indicates the PCI9080 has detected a PCI bus parity error, even if parity error handling is
disabled (the Parity Error Response bit in the Command Register is clear). One of three conditions
can cause this bit to be set:
1. PCI9080 detected a parity error during a PCI address phase.
2. PCI9080 detected a data parity error when it was the target of a write.
3. PCI9080 detected a data parity error when performing a master read.
Writing a ‘1’ to this bit clears the bit.
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