40 VMIVME-7805/VME-7805RC Hardware Reference Manual
3.2 I
2
C Support
The VMIVME-7805/VME-7805RC support the I
2
Cbus and can operate as an
I
2
Cbus master or slave per the I
2
Cbus specification, version 2.0, developed by
Philips Semiconductor. Communication over the I
2
Cbus is accomplished through
the use of the National Semiconductor Super I/O I
2
Cbus controller. This controller
is capable of communicating on the I
2
Cbus on a byte-wise basis using interrupt or
polled handshaking and supports a programmable clock rate when operating in
Master mode. The I
2
Cbus signals are available through the VMIVME-7805/
VME-7805RC E12 header as shown in Table 3-1.
The VMIVME-7805/VME-7805RC provide termination on the I
2
C signals.
The controller can issue interrupts to the VMIVME-7805/VME-7805RC when
handshaking on the I
2
Cbus. When the I
2
Cbus controller drives the interrupt
active, software must service and then clear the interrupt. Software can determine
the cause of the interrupt by reading the bit of the status register.
For more information related to programming the I
2
Cbus controller, see the
section “Access, Bus Interface (ACB)” in the
“PC87366 128-pin LPC Super I/O with
System Hardware Monitoring and MIDI and Game Ports”
datasheet available from
National Semiconductor.
Table 3-1 I
2
Cbus Through E12
Signal Name
Pin
+5.0 V
1
I2C_SDA
2
I2C_SCL
3
GND
4