Standard Features 33
Figure 2-1 Connections for the PC Interrupt Logic Controller
The PCI-to-VME Bridge has the capability of generating an NMI via the PCI
SERR# line. Table 2-6 describes the register bits that are used by the NMI. The
SERR interrupt is routed through logic back to the NMI input line on the CPU.
The CPU reads the NMI Status Control register to determine the NMI source (bits
set to 1). After the NMI interrupt routine processes the interrupt, software clears
the NMI status bits by setting the corresponding enable/disable bit to 1. The NMI
Enable and Real-Time Clock register can mask the NMI signal and disable/enable
all NMI sources.
82540 MASTER-PORTS $020-$021
IRQ0
IRQ1
IRQ2
IRQ4
IRQ5
IRQ7
Universe IIB
INTA
PCI INTERRUPT
IRQ6
IRQ3
CPU
INTR
CONNECTIONS
MAPPED BY BIOS
PMC
Site
BRIDGE
Timer
Keybd
Com 2
Com 1
Unused Floppy
Control
Interrupt
8-15
Unused
Real-Tm
Clock
Mouse
Math
AT
Flash
Hard Drv
Video,
Ethernet
Coproc
PIRQA PIRQB PIRQC PIRQD
Ethernet
INTB
INTC
INTD
MAPPER
82540 SLAVE-PORTS $0A0-$0A1
I/O Controller Hub
ICH4-M
INT
Drive
Bus
PCI-to-VME
Ethernet
IN
T
PIRQE
IRQ8
IRQ9
IRQ10
IRQ12
IRQ11
IRQ13
IRQ14
IRQ15
FPGA
IN
T
Timers/SRAM
82540EM
V
M
E
Cltr
Cltr/Sbus USB