GS66504B-EVBDB 650V
GaN E-HEMT Evaluation Board
User’s Guide
_____________________________________________________________________________________________________________________
GS66504B-EVBDB UG rev. 161120
© 2016 GaN Systems Inc.
www.gansystems.com 16
Please refer to the Evaluation Board/Kit Important Notice on page 29
Test results – GS66504B-EVBDB
Half bridge double pulse test (V
DS
=400V, I
MAX
= 15A, L=120uH, R
G(ON)
=15Ω, R
G(OFF)
=2Ω, V
GS
=+6/-3V):
Figure 15 400V/15A double pulse test waveform
Figure 15 shows the hard switching on waveforms at 400V/15A. A Vds dip can be seen due to the rising
drain current (di/dt in the power loop ΔV=Lpxdi/dt, where Lp is the total power loop inductance). After
the drain current reaches the inductor current, the Vds starts to fall. The Vgs undershoot spike is caused
by the miller feedback via Cgd under negative dv/dt.
Due to the low gate charge and small R
G(OFF)
, GaN E-HEMT gate has limited control on the turn-off
dv/dt. Instead the Vds rise time is determined by how fast the turn-off current charges switching node
capacitance (Coss).
The low Coss of GaN E-HEMT and low parasitic inductance of GaNPX™ package together with
optimized PCB alyout, enables a fast and clean turn-off Vds waveform with only 50V the turn-off Vds
overshoot at dv/dt > 100V/ns. The measured rise time is 3.9ns at 400V and 15A hard turn-off
。
